A 12.5-bit 4 MHz 13.8 mW MASH Δ Σ modulator with multirated VCO-based ADC

Samira Zaliasl; Saurabh Saxena; Pavan Kumar Hanumolu; Kartikeya Mayaram; Terri S. Fiez

doi:10.1109/TCSI.2012.2206506

A 12.5-bit 4 MHz 13.8 mW MASH Δ Σ modulator with multirated VCO-based ADC

Samira Zaliasl, Saurabh Saxena, Pavan Kumar Hanumolu, Kartikeya Mayaram, Terri S. Fiez

Research output: Contribution to journal › Article › peer-review

Abstract

A novel MASH delta-sigma Δ Σ ADC architecture is introduced that has a multirated voltage controlled oscillator (VCO)-based ADC in its second stage. The architecture allows for low power and high speed operation and is insensitive to the VCO linearity. A prototype consists of a first-order switched-capacitor (SC) modulator operating at 100 MHz in the first stage followed by a second-stage VCO-based ADC operating at 1.2 GHz. A custom IC prototype of this architecture achieves 77.3 dB signal-to-noise-ratio (SNR) over a 4 MHz signal bandwidth with a power consumption of 13.8 mW. It was fabricated in a 130 nm 1P8M CMOS process. The resulting FoM is 298 fJ per conversion.

Original language	English (US)
Article number	6243235
Pages (from-to)	1604-1613
Number of pages	10
Journal	IEEE Transactions on Circuits and Systems I: Regular Papers
Volume	59
Issue number	8
DOIs	https://doi.org/10.1109/TCSI.2012.2206506
State	Published - 2012
Externally published	Yes

Keywords

Analog to digital conversion
MASH architecture
VCO-based quantizer
delta-sigma
multirate MASH modulator

ASJC Scopus subject areas

Electrical and Electronic Engineering
Hardware and Architecture

Online availability

10.1109/TCSI.2012.2206506

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title = "A 12.5-bit 4 MHz 13.8 mW MASH Δ Σ modulator with multirated VCO-based ADC",

abstract = "A novel MASH delta-sigma Δ Σ ADC architecture is introduced that has a multirated voltage controlled oscillator (VCO)-based ADC in its second stage. The architecture allows for low power and high speed operation and is insensitive to the VCO linearity. A prototype consists of a first-order switched-capacitor (SC) modulator operating at 100 MHz in the first stage followed by a second-stage VCO-based ADC operating at 1.2 GHz. A custom IC prototype of this architecture achieves 77.3 dB signal-to-noise-ratio (SNR) over a 4 MHz signal bandwidth with a power consumption of 13.8 mW. It was fabricated in a 130 nm 1P8M CMOS process. The resulting FoM is 298 fJ per conversion.",

keywords = "Analog to digital conversion, MASH architecture, VCO-based quantizer, delta-sigma, multirate MASH modulator",

author = "Samira Zaliasl and Saurabh Saxena and Hanumolu, {Pavan Kumar} and Kartikeya Mayaram and Fiez, {Terri S.}",

note = "Funding Information: Manuscript received January 16, 2012; revised April 14, 2012; accepted April 18, 2012. Date of current version July 24, 2012. This work was supported by funding from The Space and Naval Warfare Systems Command through a subcontract from the University of Idaho. This paper was recommended by Associate Editor S. Pavan.",

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AU - Zaliasl, Samira

AU - Saxena, Saurabh

AU - Hanumolu, Pavan Kumar

AU - Mayaram, Kartikeya

AU - Fiez, Terri S.

N1 - Funding Information: Manuscript received January 16, 2012; revised April 14, 2012; accepted April 18, 2012. Date of current version July 24, 2012. This work was supported by funding from The Space and Naval Warfare Systems Command through a subcontract from the University of Idaho. This paper was recommended by Associate Editor S. Pavan.

PY - 2012

Y1 - 2012

N2 - A novel MASH delta-sigma Δ Σ ADC architecture is introduced that has a multirated voltage controlled oscillator (VCO)-based ADC in its second stage. The architecture allows for low power and high speed operation and is insensitive to the VCO linearity. A prototype consists of a first-order switched-capacitor (SC) modulator operating at 100 MHz in the first stage followed by a second-stage VCO-based ADC operating at 1.2 GHz. A custom IC prototype of this architecture achieves 77.3 dB signal-to-noise-ratio (SNR) over a 4 MHz signal bandwidth with a power consumption of 13.8 mW. It was fabricated in a 130 nm 1P8M CMOS process. The resulting FoM is 298 fJ per conversion.

AB - A novel MASH delta-sigma Δ Σ ADC architecture is introduced that has a multirated voltage controlled oscillator (VCO)-based ADC in its second stage. The architecture allows for low power and high speed operation and is insensitive to the VCO linearity. A prototype consists of a first-order switched-capacitor (SC) modulator operating at 100 MHz in the first stage followed by a second-stage VCO-based ADC operating at 1.2 GHz. A custom IC prototype of this architecture achieves 77.3 dB signal-to-noise-ratio (SNR) over a 4 MHz signal bandwidth with a power consumption of 13.8 mW. It was fabricated in a 130 nm 1P8M CMOS process. The resulting FoM is 298 fJ per conversion.

KW - Analog to digital conversion

KW - MASH architecture

KW - VCO-based quantizer

KW - delta-sigma

KW - multirate MASH modulator

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A 12.5-bit 4 MHz 13.8 mW MASH Δ Σ modulator with multirated VCO-based ADC

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