A 12.5-bit 4 MHz 13.8 mW MASH Δ Σ modulator with multirated VCO-based ADC

Samira Zaliasl, Saurabh Saxena, Pavan Kumar Hanumolu, Kartikeya Mayaram, Terri S. Fiez

Research output: Contribution to journalArticlepeer-review

Abstract

A novel MASH delta-sigma Δ Σ ADC architecture is introduced that has a multirated voltage controlled oscillator (VCO)-based ADC in its second stage. The architecture allows for low power and high speed operation and is insensitive to the VCO linearity. A prototype consists of a first-order switched-capacitor (SC) modulator operating at 100 MHz in the first stage followed by a second-stage VCO-based ADC operating at 1.2 GHz. A custom IC prototype of this architecture achieves 77.3 dB signal-to-noise-ratio (SNR) over a 4 MHz signal bandwidth with a power consumption of 13.8 mW. It was fabricated in a 130 nm 1P8M CMOS process. The resulting FoM is 298 fJ per conversion.

Original languageEnglish (US)
Article number6243235
Pages (from-to)1604-1613
Number of pages10
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume59
Issue number8
DOIs
StatePublished - Jul 25 2012
Externally publishedYes

Keywords

  • Analog to digital conversion
  • MASH architecture
  • VCO-based quantizer
  • delta-sigma
  • multirate MASH modulator

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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