A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme

Chi Sung Oh, Ki Chul Chun, Young Yong Byun, Yong Ki Kim, So Young Kim, Yesin Ryu, Jaewon Park, Sinho Kim, Sanguhn Cha, Donghak Shin, Jungyu Lee, Jong Pil Son, Byung Kyu Ho, Seong Jin Cho, Beomyong Kil, Sungoh Ahn, Baekmin Lim, Yongsik Park, Kijun Lee, Myung Kyu LeeSeungduk Baek, Junyong Noh, Jae Wook Lee, Seungseob Lee, Sooyoung Kim, Botak Lim, Seouk Kyu Choi, Jin Guk Kim, Hye In Choi, Hyuk Jun Kwon, Jun Jin Kong, Kyomin Sohn, Nam Sung Kim, Kwang Il Park, Jung Bae Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Rapidly evolving artificial intelligence (Al) technology, such as deep learning, has been successfully deployed in various applications: such as image recognition, health care, and autonomous driving. Such rapid evolution and successful deployment of Al technology have been possible owing to the emergence of accelerators, such as GPUs and TPUs, that have a higher data throughput. This, in turn, requires an enhanced memory system with large capacity and high bandwidth [1]; HBM has been the most preferred high-bandwidth memory technology due to its high-speed and low-power characteristics, and 1024 IOs facilitated by 2.5D silicon interposer technology, as well as large capacity realized by through-silicon via (TSV) stack technology [2]. Previous-generation HBM2 supports 8GB capacity with a stack of 8 DRAM dies (i.e., 8-high stack) and 341GB/s (2.7Gb/s/pin) bandwidth [3]. The HBM industry trend has been a speed improvement of 1520% every year, while capacity increases by 1.5-2x every two years. In this paper, we present a 16GB HBM2E with circuit and design techniques to increase its bandwidth up to 640GB/s (5Gb/s/pin), while providing stable bit-cell operation in the 2nd generation of a 10nm DRAM process: featuring (1) a data-bus window-extension technique to cope with reduced t {cco}, (2) a power delivery network (PDN) designed for stable operation at a high speed, (3) a synergetic on-die ECC scheme to reliably provide large capacity, and (4) an MBIST solution to efficiently test large capacity memory at a high speed.

Original languageEnglish (US)
Title of host publication2020 IEEE International Solid-State Circuits Conference, ISSCC 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages330-332
Number of pages3
ISBN (Electronic)9781728132044
DOIs
StatePublished - Feb 2020
Externally publishedYes
Event2020 IEEE International Solid-State Circuits Conference, ISSCC 2020 - San Francisco, United States
Duration: Feb 16 2020Feb 20 2020

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume2020-February
ISSN (Print)0193-6530

Conference

Conference2020 IEEE International Solid-State Circuits Conference, ISSCC 2020
CountryUnited States
CitySan Francisco
Period2/16/202/20/20

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Oh, C. S., Chun, K. C., Byun, Y. Y., Kim, Y. K., Kim, S. Y., Ryu, Y., Park, J., Kim, S., Cha, S., Shin, D., Lee, J., Son, J. P., Ho, B. K., Cho, S. J., Kil, B., Ahn, S., Lim, B., Park, Y., Lee, K., ... Lee, J. B. (2020). A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme. In 2020 IEEE International Solid-State Circuits Conference, ISSCC 2020 (pp. 330-332). [9063110] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 2020-February). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC19947.2020.9063110