A 10MS/s 11-b 0.19mm2 algorithmic ADC with improved clocking

Min Gyu Kim; Pavan Kumar Hanumolu; Un Ku Moon

A 10MS/s 11-b 0.19mm² algorithmic ADC with improved clocking

Min Gyu Kim, Pavan Kumar Hanumolu, Un Ku Moon

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A 10Ms/s 11-b algorithmic ADC with an active area of 0.19mm² is presented. Using an improved clocking scheme, this design overcomes the speed limit of algorithmic ADCs. The proposed ADC employs amplifier sharing, DC offset cancellation, and input memory effect suppression to reduce area and power, and achieve high linearity. The ADC implemented in a 0.13μm thick gate-oxide CMOS process achieves 69dB SFDR, 58dB SNR, and 56dB SNDR, while consuming 3.5mA from 3 V supply.

Original language	English (US)
Title of host publication	2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
Pages	49-50
Number of pages	2
State	Published - 2006
Externally published	Yes
Event	2006 Symposium on VLSI Circuits, VLSIC - Honolulu, HI, United States Duration: Jun 15 2006 → Jun 17 2006

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	2006 Symposium on VLSI Circuits, VLSIC
Country/Territory	United States
City	Honolulu, HI
Period	6/15/06 → 6/17/06

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Library availability

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Cite this

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title = "A 10MS/s 11-b 0.19mm2 algorithmic ADC with improved clocking",

abstract = "A 10Ms/s 11-b algorithmic ADC with an active area of 0.19mm2 is presented. Using an improved clocking scheme, this design overcomes the speed limit of algorithmic ADCs. The proposed ADC employs amplifier sharing, DC offset cancellation, and input memory effect suppression to reduce area and power, and achieve high linearity. The ADC implemented in a 0.13μm thick gate-oxide CMOS process achieves 69dB SFDR, 58dB SNR, and 56dB SNDR, while consuming 3.5mA from 3 V supply.",

author = "Kim, {Min Gyu} and Hanumolu, {Pavan Kumar} and Moon, {Un Ku}",

year = "2006",

language = "English (US)",

isbn = "1424400066",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

pages = "49--50",

booktitle = "2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers",

note = "2006 Symposium on VLSI Circuits, VLSIC ; Conference date: 15-06-2006 Through 17-06-2006",

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AU - Kim, Min Gyu

AU - Hanumolu, Pavan Kumar

AU - Moon, Un Ku

PY - 2006

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N2 - A 10Ms/s 11-b algorithmic ADC with an active area of 0.19mm2 is presented. Using an improved clocking scheme, this design overcomes the speed limit of algorithmic ADCs. The proposed ADC employs amplifier sharing, DC offset cancellation, and input memory effect suppression to reduce area and power, and achieve high linearity. The ADC implemented in a 0.13μm thick gate-oxide CMOS process achieves 69dB SFDR, 58dB SNR, and 56dB SNDR, while consuming 3.5mA from 3 V supply.

AB - A 10Ms/s 11-b algorithmic ADC with an active area of 0.19mm2 is presented. Using an improved clocking scheme, this design overcomes the speed limit of algorithmic ADCs. The proposed ADC employs amplifier sharing, DC offset cancellation, and input memory effect suppression to reduce area and power, and achieve high linearity. The ADC implemented in a 0.13μm thick gate-oxide CMOS process achieves 69dB SFDR, 58dB SNR, and 56dB SNDR, while consuming 3.5mA from 3 V supply.

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M3 - Conference contribution

AN - SCOPUS:39749135613

SN - 1424400066

SN - 9781424400065

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

SP - 49

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BT - 2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers

T2 - 2006 Symposium on VLSI Circuits, VLSIC

Y2 - 15 June 2006 through 17 June 2006

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