A 10MS/s 11-b 0.19mm2 algorithmic ADC with improved clocking

Min Gyu Kim, Pavan Kumar Hanumolu, Un Ku Moon

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A 10Ms/s 11-b algorithmic ADC with an active area of 0.19mm2 is presented. Using an improved clocking scheme, this design overcomes the speed limit of algorithmic ADCs. The proposed ADC employs amplifier sharing, DC offset cancellation, and input memory effect suppression to reduce area and power, and achieve high linearity. The ADC implemented in a 0.13μm thick gate-oxide CMOS process achieves 69dB SFDR, 58dB SNR, and 56dB SNDR, while consuming 3.5mA from 3 V supply.

Original languageEnglish (US)
Title of host publication2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
Pages49-50
Number of pages2
StatePublished - Dec 1 2006
Externally publishedYes
Event2006 Symposium on VLSI Circuits, VLSIC - Honolulu, HI, United States
Duration: Jun 15 2006Jun 17 2006

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2006 Symposium on VLSI Circuits, VLSIC
CountryUnited States
CityHonolulu, HI
Period6/15/066/17/06

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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