A 10.3GS/s 6bit (5.1 ENOB at Nyquist) time-interleaved/pipelined ADC using open-loop amplifiers and digital calibration in 90nm CMOS

Ali Nazemi; Carl Grace; Lanny Lewyn; Bilal Kobeissy; Oscar Agazzi; Paul Voois; Cindra Abidin; George Eaton; Mahyar Kargar; Cesar Marquez; Sumant Ramprasad; Federico Bollo; Vladimir A. Posse; Stephen Wang; Georgios Asmanis

doi:10.1109/VLSIC.2008.4585935

A 10.3GS/s 6bit (5.1 ENOB at Nyquist) time-interleaved/pipelined ADC using open-loop amplifiers and digital calibration in 90nm CMOS

Ali Nazemi, Carl Grace, Lanny Lewyn, Bilal Kobeissy, Oscar Agazzi, Paul Voois, Cindra Abidin, George Eaton, Mahyar Kargar, Cesar Marquez, Sumant Ramprasad, Federico Bollo, Vladimir A. Posse, Stephen Wang, Georgios Asmanis

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A 10.3GS/s ADC with 5GHz input BW and 6 bit resolution in 90nm CMOS is presented. The architecture is based on an 8 way interleaved/ pipelined ADC using open-loop amplifiers and digital calibration. The measured performance is 5.8 ENOB (36.6dB SNDR) for a 100MHz input signal and 5.1 ENOB (32.4dB SNDR) for a 5GHz input (Nyquist) with phase offset correction across the interleaved array.

Original language	English (US)
Title of host publication	2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC
Pages	18-19
Number of pages	2
DOIs	https://doi.org/10.1109/VLSIC.2008.4585935
State	Published - Sep 23 2008
Externally published	Yes
Event	2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC - Honolulu, HI, United States Duration: Jun 18 2008 → Jun 20 2008

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC
Country/Territory	United States
City	Honolulu, HI
Period	6/18/08 → 6/20/08

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Online availability

10.1109/VLSIC.2008.4585935

Library availability

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Nazemi, A., Grace, C., Lewyn, L., Kobeissy, B., Agazzi, O., Voois, P., Abidin, C., Eaton, G., Kargar, M., Marquez, C., Ramprasad, S., Bollo, F., Posse, V. A., Wang, S., & Asmanis, G. (2008). A 10.3GS/s 6bit (5.1 ENOB at Nyquist) time-interleaved/pipelined ADC using open-loop amplifiers and digital calibration in 90nm CMOS. In 2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC (pp. 18-19). Article 4585935 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). https://doi.org/10.1109/VLSIC.2008.4585935

A 10.3GS/s 6bit (5.1 ENOB at Nyquist) time-interleaved/pipelined ADC using open-loop amplifiers and digital calibration in 90nm CMOS. / Nazemi, Ali; Grace, Carl; Lewyn, Lanny et al.
2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC. 2008. p. 18-19 4585935 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Nazemi, A, Grace, C, Lewyn, L, Kobeissy, B, Agazzi, O, Voois, P, Abidin, C, Eaton, G, Kargar, M, Marquez, C, Ramprasad, S, Bollo, F, Posse, VA, Wang, S & Asmanis, G 2008, A 10.3GS/s 6bit (5.1 ENOB at Nyquist) time-interleaved/pipelined ADC using open-loop amplifiers and digital calibration in 90nm CMOS. in 2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC., 4585935, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 18-19, 2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC, Honolulu, HI, United States, 6/18/08. https://doi.org/10.1109/VLSIC.2008.4585935

Nazemi A, Grace C, Lewyn L, Kobeissy B, Agazzi O, Voois P et al. A 10.3GS/s 6bit (5.1 ENOB at Nyquist) time-interleaved/pipelined ADC using open-loop amplifiers and digital calibration in 90nm CMOS. In 2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC. 2008. p. 18-19. 4585935. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.1109/VLSIC.2008.4585935

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abstract = "A 10.3GS/s ADC with 5GHz input BW and 6 bit resolution in 90nm CMOS is presented. The architecture is based on an 8 way interleaved/ pipelined ADC using open-loop amplifiers and digital calibration. The measured performance is 5.8 ENOB (36.6dB SNDR) for a 100MHz input signal and 5.1 ENOB (32.4dB SNDR) for a 5GHz input (Nyquist) with phase offset correction across the interleaved array.",

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AU - Kobeissy, Bilal

AU - Agazzi, Oscar

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AU - Abidin, Cindra

AU - Eaton, George

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A 10.3GS/s 6bit (5.1 ENOB at Nyquist) time-interleaved/pipelined ADC using open-loop amplifiers and digital calibration in 90nm CMOS

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