@inproceedings{61f830ff6ecd4758960c83fe8c7d0a4e,
title = "A 10.3GS/s 6bit (5.1 ENOB at Nyquist) time-interleaved/pipelined ADC using open-loop amplifiers and digital calibration in 90nm CMOS",
abstract = "A 10.3GS/s ADC with 5GHz input BW and 6 bit resolution in 90nm CMOS is presented. The architecture is based on an 8 way interleaved/ pipelined ADC using open-loop amplifiers and digital calibration. The measured performance is 5.8 ENOB (36.6dB SNDR) for a 100MHz input signal and 5.1 ENOB (32.4dB SNDR) for a 5GHz input (Nyquist) with phase offset correction across the interleaved array.",
author = "Ali Nazemi and Carl Grace and Lanny Lewyn and Bilal Kobeissy and Oscar Agazzi and Paul Voois and Cindra Abidin and George Eaton and Mahyar Kargar and Cesar Marquez and Sumant Ramprasad and Federico Bollo and Posse, {Vladimir A.} and Stephen Wang and Georgios Asmanis",
year = "2008",
month = sep,
day = "23",
doi = "10.1109/VLSIC.2008.4585935",
language = "English (US)",
isbn = "9781424418053",
series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",
pages = "18--19",
booktitle = "2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC",
note = "2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC ; Conference date: 18-06-2008 Through 20-06-2008",
}