A 10.3GS/s 6bit (5.1 ENOB at Nyquist) time-interleaved/pipelined ADC using open-loop amplifiers and digital calibration in 90nm CMOS

Ali Nazemi, Carl Grace, Lanny Lewyn, Bilal Kobeissy, Oscar Agazzi, Paul Voois, Cindra Abidin, George Eaton, Mahyar Kargar, Cesar Marquez, Sumant Ramprasad, Federico Bollo, Vladimir A. Posse, Stephen Wang, Georgios Asmanis

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A 10.3GS/s ADC with 5GHz input BW and 6 bit resolution in 90nm CMOS is presented. The architecture is based on an 8 way interleaved/ pipelined ADC using open-loop amplifiers and digital calibration. The measured performance is 5.8 ENOB (36.6dB SNDR) for a 100MHz input signal and 5.1 ENOB (32.4dB SNDR) for a 5GHz input (Nyquist) with phase offset correction across the interleaved array.

Original languageEnglish (US)
Title of host publication2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC
Pages18-19
Number of pages2
DOIs
StatePublished - Sep 23 2008
Externally publishedYes
Event2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC - Honolulu, HI, United States
Duration: Jun 18 2008Jun 20 2008

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC
CountryUnited States
CityHonolulu, HI
Period6/18/086/20/08

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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