A 10 MS/s 11-bit 0.19 mm2 algorithmic ADC with improved clocking scheme

Min Gyu Kim; Pavan Kumar Hanumolu; Un Ku Moon

doi:10.1109/JSSC.2009.2023158

A 10 MS/s 11-bit 0.19 mm² algorithmic ADC with improved clocking scheme

Min Gyu Kim, Pavan Kumar Hanumolu, Un Ku Moon

Research output: Contribution to journal › Article › peer-review

Abstract

A 10 MS/s 11-bit algorithmic ADC with an active area of 0.19∼ mm 2 is presented. Using an improved clocking scheme, this design overcomes the speed limit of algorithmic ADCs. The proposed ADC employs amplifier sharing, DC offset cancellation, and input memory effect suppression, resulting in reduced area and power, and high linearity. The ADC implemented in a 0.13∼μ m thick gate-oxide CMOS process achieves 69 dB SFDR, 58 dB SNR, and 56 dB SNDR, while consuming 3.5 mA from a 3 V supply.

Original language	English (US)
Article number	5226753
Pages (from-to)	2348-2355
Number of pages	8
Journal	IEEE Journal of Solid-State Circuits
Volume	44
Issue number	9
DOIs	https://doi.org/10.1109/JSSC.2009.2023158
State	Published - Sep 2009
Externally published	Yes

Keywords

Algorithmic ADC
Amp sharing
Clocking scheme
Delay-locked loop
Memory effect
System-on-chip

ASJC Scopus subject areas

Electrical and Electronic Engineering

Online availability

10.1109/JSSC.2009.2023158

Library availability

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Cite this

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title = "A 10 MS/s 11-bit 0.19 mm2 algorithmic ADC with improved clocking scheme",

abstract = "A 10 MS/s 11-bit algorithmic ADC with an active area of 0.19∼ mm 2 is presented. Using an improved clocking scheme, this design overcomes the speed limit of algorithmic ADCs. The proposed ADC employs amplifier sharing, DC offset cancellation, and input memory effect suppression, resulting in reduced area and power, and high linearity. The ADC implemented in a 0.13∼μ m thick gate-oxide CMOS process achieves 69 dB SFDR, 58 dB SNR, and 56 dB SNDR, while consuming 3.5 mA from a 3 V supply.",

keywords = "Algorithmic ADC, Amp sharing, Clocking scheme, Delay-locked loop, Memory effect, System-on-chip",

author = "Kim, {Min Gyu} and Hanumolu, {Pavan Kumar} and Moon, {Un Ku}",

note = "Funding Information: Manuscript received December 10, 2008. Current version published August 26, 2009. This work was supported by the Center for Design of Analog-Digital Integrated Circuits (CDADIC), and in part by Samsung Electronics.",

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