A 10 MS/s 11-bit 0.19 mm2 algorithmic ADC with improved clocking scheme

Min Gyu Kim, Pavan Kumar Hanumolu, Un Ku Moon

Research output: Contribution to journalArticle

Abstract

A 10 MS/s 11-bit algorithmic ADC with an active area of 0.19∼ mm 2 is presented. Using an improved clocking scheme, this design overcomes the speed limit of algorithmic ADCs. The proposed ADC employs amplifier sharing, DC offset cancellation, and input memory effect suppression, resulting in reduced area and power, and high linearity. The ADC implemented in a 0.13∼μ m thick gate-oxide CMOS process achieves 69 dB SFDR, 58 dB SNR, and 56 dB SNDR, while consuming 3.5 mA from a 3 V supply.

Original languageEnglish (US)
Article number5226753
Pages (from-to)2348-2355
Number of pages8
JournalIEEE Journal of Solid-State Circuits
Volume44
Issue number9
DOIs
StatePublished - Sep 1 2009
Externally publishedYes

Keywords

  • Algorithmic ADC
  • Amp sharing
  • Clocking scheme
  • Delay-locked loop
  • Memory effect
  • System-on-chip

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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