A 10-Gb/s/ch, 0.6-pJ/bit/mm Power Scalable Rapid-ON/OFF Transceiver for On-Chip Energy Proportional Interconnects

Modern multiprocessor system-on-chips employ network-on-chip (NoC) to efficiently connect different components together. NoCs need global and local interconnects to deliver high on-chip bandwidth and low communication latency to avoid being a performance bottleneck. They must also have high throughput density to reduce area occupied by wires. This paper presents techniques to implement power efficient transceivers for on-chip links that can achieve energy proportional operation. Conventional on-chip links optimized for best energy efficiency at peak data rate suffer from degraded energy efficiency under low utilization conditions. Dynamic voltage and frequency scaling and clock gating can partially alleviate this problem, but become ineffective in applications like mobile devices, where the data traffic can be very sporadic. In this paper, architecture and circuit techniques to improve energy efficiency under all utilization levels are presented. The proposed transceiver uses single-ended signaling with only 0.5m width and spacing and achieves 5-Gb/m throughput density. Fast locking signaling and clocking circuits greatly reduce the power-ON time. Fabricated in 65-nm CMOS technology, the proposed 10-Gb/s transceiver achieves wake-up time in less than 17 ns. More than 125× effective data rate scaling (10 Gb/s to 80 Mb/s) is obtained with an energy efficiency degradation of only 1.6× (627 to 997 fJ/b/mm). When the supply voltage is scaled from 1 to 0.7 V, the peak data rate scales from 10 to 6 Gb/s and the power scalable range increases to 208× (10 Gb/s to 48 Mb/s) with the energy efficiency degradation of only 1.2× (627 to 753 fJ/b/mm).