Abstract
A 10 Gb/s adaptive analog decision feedback equalizer with 6 taps is realized in 0.13 µm CMOS. An analog implementation of the LMS algorithm is used to continuously adapt the feedback filter coefficients. A clock and data recovery circuit is used to extract the clock from the DFE output. The adaptive DFE dissipates 318 mW, not including output buffers, and can equalize PRBS data corrupted by a 300-m multimode fiber achieving BER <10-13.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 271-283 |
| Number of pages | 13 |
| Journal | Analog Integrated Circuits and Signal Processing |
| Volume | 83 |
| Issue number | 2 |
| DOIs | |
| State | Published - May 1 2015 |
| Externally published | Yes |
Keywords
- Binary phase detectors
- Broadband communications
- Clock data recovery
- CMOS
- Decision feedback equalizers
- Integrated circuits
ASJC Scopus subject areas
- Signal Processing
- Hardware and Architecture
- Surfaces, Coatings and Films