A 10-b statistical ADC employing pipelining and sub-ranging in 32nm CMOS

Sen Tao, Naveen Verma, Ryan M. Corey, Andrew Carl Singer

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a 10-b statistical ADC (S-ADC), achieving higher resolution (INL) than any previously reported S-ADC. This resolution requires a large number of statistical observations via comparators (12k) with offset variation, making code estimation a key challenge. The efficiency of estimation is enhanced by a coarse frontend estimator, employing pipelining and sub-ranging to arrive at a reduced range, which is then provided to a fine backend estimator. The total computations are reduced by 19×, compared to single-stage estimation over the entire analog range. Implemented in a 32nm process, the S-ADC achieves INL<1.73 LSB and total code estimation error (non-linearity and noise) <2.3 LSBrms. Designed to run at 20MHz, excess supply impedance limits comparator speed to 2MHz. The energy per 10-b conversion for the comparator array (at 2MHz) is 744 pJ and the energy per 10-b conversion of the digital estimator (at 20MHz) is 627 pJ.

Original languageEnglish (US)
Title of host publicationIEEE International Symposium on Circuits and Systems
Subtitle of host publicationFrom Dreams to Innovation, ISCAS 2017 - Conference Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467368520
DOIs
StatePublished - Sep 25 2017
Event50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 - Baltimore, United States
Duration: May 28 2017May 31 2017

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Other

Other50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
CountryUnited States
CityBaltimore
Period5/28/175/31/17

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Error analysis

Keywords

  • Analog-digital conversion
  • analog-digital integrated circuits
  • estimation
  • statistical distributions

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Tao, S., Verma, N., Corey, R. M., & Singer, A. C. (2017). A 10-b statistical ADC employing pipelining and sub-ranging in 32nm CMOS. In IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings [8050245] (Proceedings - IEEE International Symposium on Circuits and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2017.8050245

A 10-b statistical ADC employing pipelining and sub-ranging in 32nm CMOS. / Tao, Sen; Verma, Naveen; Corey, Ryan M.; Singer, Andrew Carl.

IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. 8050245 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Tao, S, Verma, N, Corey, RM & Singer, AC 2017, A 10-b statistical ADC employing pipelining and sub-ranging in 32nm CMOS. in IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings., 8050245, Proceedings - IEEE International Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers Inc., 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, United States, 5/28/17. https://doi.org/10.1109/ISCAS.2017.8050245
Tao S, Verma N, Corey RM, Singer AC. A 10-b statistical ADC employing pipelining and sub-ranging in 32nm CMOS. In IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc. 2017. 8050245. (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2017.8050245
Tao, Sen ; Verma, Naveen ; Corey, Ryan M. ; Singer, Andrew Carl. / A 10-b statistical ADC employing pipelining and sub-ranging in 32nm CMOS. IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. (Proceedings - IEEE International Symposium on Circuits and Systems).
@inproceedings{c6cbb447eb9c47b085e7027b07427244,
title = "A 10-b statistical ADC employing pipelining and sub-ranging in 32nm CMOS",
abstract = "This paper presents a 10-b statistical ADC (S-ADC), achieving higher resolution (INL) than any previously reported S-ADC. This resolution requires a large number of statistical observations via comparators (12k) with offset variation, making code estimation a key challenge. The efficiency of estimation is enhanced by a coarse frontend estimator, employing pipelining and sub-ranging to arrive at a reduced range, which is then provided to a fine backend estimator. The total computations are reduced by 19×, compared to single-stage estimation over the entire analog range. Implemented in a 32nm process, the S-ADC achieves INL<1.73 LSB and total code estimation error (non-linearity and noise) <2.3 LSBrms. Designed to run at 20MHz, excess supply impedance limits comparator speed to 2MHz. The energy per 10-b conversion for the comparator array (at 2MHz) is 744 pJ and the energy per 10-b conversion of the digital estimator (at 20MHz) is 627 pJ.",
keywords = "Analog-digital conversion, analog-digital integrated circuits, estimation, statistical distributions",
author = "Sen Tao and Naveen Verma and Corey, {Ryan M.} and Singer, {Andrew Carl}",
year = "2017",
month = "9",
day = "25",
doi = "10.1109/ISCAS.2017.8050245",
language = "English (US)",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "IEEE International Symposium on Circuits and Systems",
address = "United States",

}

TY - GEN

T1 - A 10-b statistical ADC employing pipelining and sub-ranging in 32nm CMOS

AU - Tao, Sen

AU - Verma, Naveen

AU - Corey, Ryan M.

AU - Singer, Andrew Carl

PY - 2017/9/25

Y1 - 2017/9/25

N2 - This paper presents a 10-b statistical ADC (S-ADC), achieving higher resolution (INL) than any previously reported S-ADC. This resolution requires a large number of statistical observations via comparators (12k) with offset variation, making code estimation a key challenge. The efficiency of estimation is enhanced by a coarse frontend estimator, employing pipelining and sub-ranging to arrive at a reduced range, which is then provided to a fine backend estimator. The total computations are reduced by 19×, compared to single-stage estimation over the entire analog range. Implemented in a 32nm process, the S-ADC achieves INL<1.73 LSB and total code estimation error (non-linearity and noise) <2.3 LSBrms. Designed to run at 20MHz, excess supply impedance limits comparator speed to 2MHz. The energy per 10-b conversion for the comparator array (at 2MHz) is 744 pJ and the energy per 10-b conversion of the digital estimator (at 20MHz) is 627 pJ.

AB - This paper presents a 10-b statistical ADC (S-ADC), achieving higher resolution (INL) than any previously reported S-ADC. This resolution requires a large number of statistical observations via comparators (12k) with offset variation, making code estimation a key challenge. The efficiency of estimation is enhanced by a coarse frontend estimator, employing pipelining and sub-ranging to arrive at a reduced range, which is then provided to a fine backend estimator. The total computations are reduced by 19×, compared to single-stage estimation over the entire analog range. Implemented in a 32nm process, the S-ADC achieves INL<1.73 LSB and total code estimation error (non-linearity and noise) <2.3 LSBrms. Designed to run at 20MHz, excess supply impedance limits comparator speed to 2MHz. The energy per 10-b conversion for the comparator array (at 2MHz) is 744 pJ and the energy per 10-b conversion of the digital estimator (at 20MHz) is 627 pJ.

KW - Analog-digital conversion

KW - analog-digital integrated circuits

KW - estimation

KW - statistical distributions

UR - http://www.scopus.com/inward/record.url?scp=85032686293&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85032686293&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2017.8050245

DO - 10.1109/ISCAS.2017.8050245

M3 - Conference contribution

AN - SCOPUS:85032686293

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

BT - IEEE International Symposium on Circuits and Systems

PB - Institute of Electrical and Electronics Engineers Inc.

ER -