A 0.9V 92dB double-sampled switched-RC ΔΣ audio ADC

Min Gyu Kim, Gil Cho Ahn, Pavan Kumar Hanumolu, Sang Hyeon Lee, Sang Ho Kim, Seung Bin You, Jae Whui Kim, Gabor C. Temes, Un Ku Moon

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A 0.9V third-order 1.5bit delta-sigma ADC with simple dynamic element matching (DEM) is presented. A fully-differential low-voltage double-sampling structure avoids use of clock boosting or bootstrapping. It operates from 0.65V to 1.5V supply with minimal performance degradation. The prototype IC implemented in a 0.13μm CMOS process achieves 92dB DR, 91dB SNR and 89dB SNDR, while consuming 1.5mW from a 0.9V supply.

Original languageEnglish (US)
Title of host publication2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
Pages160-161
Number of pages2
StatePublished - 2006
Externally publishedYes
Event2006 Symposium on VLSI Circuits, VLSIC - Honolulu, HI, United States
Duration: Jun 15 2006Jun 17 2006

Other

Other2006 Symposium on VLSI Circuits, VLSIC
Country/TerritoryUnited States
CityHonolulu, HI
Period6/15/066/17/06

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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