A 0.9 V 92 dB double-sampled switched-RC delta-sigma audio ADC

Min Gyu Kim, Gil Cho Ahn, Pavan Kumar Hanumolu, Sang Hyeon Lee, Sang Ho Kim, Seung Bin You, Jae Whui Kim, Gabor C. Temes, Un Ku Moon

Research output: Contribution to journalArticle

Abstract

A 0.9 V third-order double-sampled delta-sigma audio ADC is presented. A new method using a combination of a switched-RC technique and a floating switched-capacitor double-sampling configuration enabled low-voltage operation without clock boosting or bootstrapping. A three-level quantizer with simple dynamic element matching was used to improve linearity. The prototype IC implemented in a 0.13 μm CMOS process achieves 92 dB DR, 91 dB SNR and 89 dB SNDR in a 24 kHz audio signal bandwidth, while consuming 1.5 mW from a 0.9 V supply. The prototype operates from 0.65 V to 1.5 V supply with minimal performance degradation.

Original languageEnglish (US)
Article number4494661
Pages (from-to)1195-1205
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Volume43
Issue number5
DOIs
StatePublished - May 1 2008
Externally publishedYes

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Keywords

  • Audio ADC
  • Delta-sigma ADC
  • Double sampling
  • Low voltage
  • Switched-RC

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Kim, M. G., Ahn, G. C., Hanumolu, P. K., Lee, S. H., Kim, S. H., You, S. B., Kim, J. W., Temes, G. C., & Moon, U. K. (2008). A 0.9 V 92 dB double-sampled switched-RC delta-sigma audio ADC. IEEE Journal of Solid-State Circuits, 43(5), 1195-1205. [4494661]. https://doi.org/10.1109/JSSC.2008.920329