A 0.79 pJ/K-Gate, 83% efficient unified core and voltage regulator architecture for sub/near-threshold operation in 130 nm CMOS

Sai Zhang, Jane S. Tu, Naresh R Shanbhag, Philip T Krein

Research output: Contribution to journalArticle

Abstract

This paper presents the compute voltage regulator module (C-VRM), an architecture that embeds the information processing subsystem into the energy delivery subsystem for ultra-low power (ULP) platforms. The C-VRM employs multiple voltage domain stacking and core swapping to achieve high total system energy efficiency in near/sub-threshold region. Energy models for the C-VRM are derived, and employed in system simulations to compare the energy efficiency benefits of the C-VRM over a switched capacitor VRM (SC-VRM). A prototype IC incorporating a C-VRM and a SC-VRM supplying energy to an 8-tap fully folded FIR filter core is implemented in a 1.2 V, 130 nm CMOS process. Measured results indicate that the C-VRM has up to 44.8% savings in system-level energy per operation (Eop}) compared to the SC-VRM system, and an efficiency η ranging from 79% to 83% over an output voltage range of 0.52 V to 0.6 V. Measured values of the Eop and η match those predicted by system simulations thereby validating the energy models.

Original languageEnglish (US)
Article number6901296
Pages (from-to)2644-2657
Number of pages14
JournalIEEE Journal of Solid-State Circuits
Volume49
Issue number11
DOIs
StatePublished - Nov 1 2014

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Keywords

  • Energy efficient digital
  • VLSI architecture
  • low power
  • sub/near threshold
  • voltage regulator

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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