A 0.7-to-3.5 GHz 0.6-to-2.8 mW highly digital phase-locked loop with bandwidth tracking

A digital phase-locked loop (DPLL) employs a linear proportional path, a double integral path, bandwidth and tuning range tracking; and a novel delta-sigma digital to analog converter to achieve low jitter, wide operating range and low power. The proposed proportional path decouples the detector quantization error and oscillator noise bandwidth tradeoff and helps maximize bandwidth to suppress digitally controlled oscillator (DCO) phase noise in a power efficient manner. A double integral path alleviates the tradeoff between DCO tuning range and its frequency quantization error. The high resolution of the DCO was maintained over a wide range of sampling clock frequencies by using a delta-sigma digital to analog converter and a continuously tunable switched-RC filter. Bandwidth and tuning range tracking are employed to achieve low jitter over the entire operating range. The prototype DPLL, fabricated in a 90 nm CMOS process, operates from 0.7 GHz to 3.5 GHz. At 2.5 GHz, the proposed DPLL consumes only 1.6 mW power from a 1 V supply and achieves 1.6 ps and 11.6 ps of long-term r.m.s and peak jitter, respectively.