A 0.5-to-2.5GHz supply-regulated PLL with noise sensitivity of -28dB

Abhijith Arakali, Srikanth Gondi, Pavan Kumar Hanumolu

Research output: Contribution to journalConference articlepeer-review


A supply-regulated phase-locked loop (PLL) employs a split-tuned architecture to decouple the tradeoff between supply-noise rejection performance and power consumption. The prototype PLL, incorporating a novel regulator, is fabricated in a 0.18μm digital CMOS process and operates from 0.5 to 2.5GHz. At 1.5GHz, the proposed PLL achieves a worst-case noise sensitivity of -28dB (0.5rad/V), an improvement of 20dB over conventional solutions, while consuming 2.2mA from a 1.8V supply.

Original languageEnglish (US)
Article number4672116
Pages (from-to)443-446
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
StatePublished - Dec 26 2008
Externally publishedYes
EventIEEE 2008 Custom Integrated Circuits Conference, CICC 2008 - San Jose, CA, United States
Duration: Sep 21 2008Sep 24 2008

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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