TY - GEN
T1 - A 0.5 to 2.5GHz PLL with fully differential supply-regulated tuning
AU - Brownlee, Merrick
AU - Hanumolu, Pavan Kumar
AU - Mayaram, Kartikeya
AU - Moon, Un Ku
PY - 2006
Y1 - 2006
N2 - A PLL uses a fully differential supply-regulated tuning scheme to combat power-supply noise. The charge pump uses a resistor to set the current and reduce the flicker noise corner. Fabricated in a 0.18μm CMOS process, the PLL area is 0.15mm2. Operating at 2.4GHz, it has 3.29psrms jitter, a frequency range of 0.5 to 2.5GHz, and draws 14mA from a 1.8V supply.
AB - A PLL uses a fully differential supply-regulated tuning scheme to combat power-supply noise. The charge pump uses a resistor to set the current and reduce the flicker noise corner. Fabricated in a 0.18μm CMOS process, the PLL area is 0.15mm2. Operating at 2.4GHz, it has 3.29psrms jitter, a frequency range of 0.5 to 2.5GHz, and draws 14mA from a 1.8V supply.
UR - http://www.scopus.com/inward/record.url?scp=33845675538&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=33845675538&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:33845675538
SN - 1424400791
SN - 9781424400799
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 588+585
BT - 2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
T2 - 2006 IEEE International Solid-State Circuits Conference, ISSCC
Y2 - 6 February 2006 through 9 February 2006
ER -