TY - GEN
T1 - A 0.5-to-2.5Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance
AU - Inti, Rajesh
AU - Yin, Wenjing
AU - Elshazly, Amr
AU - Sasidhar, Naga
AU - Hanumolu, Pavan Kumar
PY - 2011
Y1 - 2011
N2 - Clock and data recovery (CDR) circuits with wide frequency acquisition range offer flexibility in optical communication networks, help reduce link power through activity-based rate adaptation, and minimize cost with a single-chip multi-standard solution. Extracting the bit rate from the incoming random data stream is the main challenge in implementing reference-less CDRs. A conventional rotational frequency detector has a limited acquisition range of about ±50% of the VCO frequency, consumes large power, and is susceptible to harmonic locking. Extending its range requires additional high-speed circuitry and a complex state machine [1]. The DLL-based architecture in [2] requires passing high-speed data through a long string of power-hungry buffers, imposes stringent matching requirements, and works only with ring oscillators. Other approaches require detailed statistical [3] or timing analysis [4]. Further, all the above techniques are only suitable for full-rate CDRs. In this paper, we present a reference-less half-rate CDR that uses a sub-harmonic extraction method to achieve unlimited frequency acquisition range. This technique is capable of locking the CDR to within 40ppm of any sub-rate of the data (making it applicable for any sub-rate CDR architecture), while being immune to undesirable harmonic locking. This CDR also integrates a calibration loop to improve robustness to input duty cycle error.
AB - Clock and data recovery (CDR) circuits with wide frequency acquisition range offer flexibility in optical communication networks, help reduce link power through activity-based rate adaptation, and minimize cost with a single-chip multi-standard solution. Extracting the bit rate from the incoming random data stream is the main challenge in implementing reference-less CDRs. A conventional rotational frequency detector has a limited acquisition range of about ±50% of the VCO frequency, consumes large power, and is susceptible to harmonic locking. Extending its range requires additional high-speed circuitry and a complex state machine [1]. The DLL-based architecture in [2] requires passing high-speed data through a long string of power-hungry buffers, imposes stringent matching requirements, and works only with ring oscillators. Other approaches require detailed statistical [3] or timing analysis [4]. Further, all the above techniques are only suitable for full-rate CDRs. In this paper, we present a reference-less half-rate CDR that uses a sub-harmonic extraction method to achieve unlimited frequency acquisition range. This technique is capable of locking the CDR to within 40ppm of any sub-rate of the data (making it applicable for any sub-rate CDR architecture), while being immune to undesirable harmonic locking. This CDR also integrates a calibration loop to improve robustness to input duty cycle error.
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U2 - 10.1109/ISSCC.2011.5746387
DO - 10.1109/ISSCC.2011.5746387
M3 - Conference contribution
AN - SCOPUS:79955718509
SN - 9781612843001
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 438
EP - 439
BT - 2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2011 IEEE International Solid-State Circuits Conference, ISSCC 2011
Y2 - 20 February 2011 through 24 February 2011
ER -