A 0.5-to-2.5 Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance

Rajesh Inti, Wenjing Yin, Amr Elshazly, Naga Sasidhar, Pavan Kumar Hanumolu

Research output: Contribution to journalArticle


A reference-less highly digital half-rate clock and data recovery (CDR) circuit with improved tolerance to input duty cycle error is presented. Using a chain of frequency dividers, the proposed frequency detector produces a known sub-harmonic tone from the incoming random data. A digital frequency-locked loop uses the extracted tone, and drives the oscillator to any sub-rate of the input data frequency. The early/late outputs of a conventional half-rate bang-bang phase detector are used to determine the duty-cycle error in the incoming random data and adjust the oscillator clock phases to maximize receiver timing margins. Fabricated in 0.13 μm CMOS technology, the prototype digital CDR operates without any errors from 0.5 Gb/s to 2.5 Gb/s. At 2 Gb/s, the prototype consumes 6.1 mW power from a 1.2 V supply. The proposed clock-phase calibration is capable of correcting upto ±20% of input data duty-cycle error.

Original languageEnglish (US)
Article number6069580
Pages (from-to)3150-3162
Number of pages13
JournalIEEE Journal of Solid-State Circuits
Issue number12
StatePublished - Dec 1 2011



  • Digital CDR
  • clock phase calibration
  • data duty cycle error
  • linear delay cell
  • optimal sampling
  • power spectral density of random NRZ data
  • reference-less frequency acquisition

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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