A 0.5-GHz to 2.5-GHz PLL with fully differential supply regulated tuning

Keyphrases

• Phase-locked Loop 100%
• Fully Differential 100%
• Charge Pump 66%
• Resistors 33%
• Current Source 33%
• Flicker Noise 33%
• Power Consumption 33%
• Jitter 33%
• Die Area 33%
• CMOS Process 33%
• Power Supply Noise 33%
• Tuning Scheme 33%
• Pump Current 33%
• Clock Generation 33%
• Active Current 33%

Engineering

• Phase Locked Loop 100%
• Charge Pump 66%
• Power Supply 33%
• Current Source 33%
• Flicker Noise 33%
• Electric Power Utilization 33%