A 0.5-GHz to 2.5-GHz PLL with fully differential supply regulated tuning

Merrick Brownlee; Pavan Kumar Hanumolu; Kartikeya Mayaram; Un Ku Moon

doi:10.1109/JSSC.2006.884194

A 0.5-GHz to 2.5-GHz PLL with fully differential supply regulated tuning

Merrick Brownlee, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un Ku Moon

Research output: Contribution to journal › Article › peer-review

Abstract

This paper describes a wide-range clock generation phase-locked loop (PLL) incorporating several features that make it suitable for integration in highly scaled processes. A fully differential supply regulated tuning scheme is used to combat power supply noise. The charge pump uses a resistor rather than an active current source to define the pumping current in order to reduce the charge pump flicker noise. Fabricated in a 0.18-μm CMOS process, the PLL occupies 0.15 mm ² die area and achieves a frequency range of 0.5 to 2.5 GHz. When operating at 2.4 GHz, the power consumption is 14 mA from a 1.8-V supply while the jitter is 2.36 ps rms.

Original language	English (US)
Pages (from-to)	2720-2727
Number of pages	8
Journal	IEEE Journal of Solid-State Circuits
Volume	41
Issue number	12
DOIs	https://doi.org/10.1109/JSSC.2006.884194
State	Published - Dec 2006
Externally published	Yes

Keywords

Charge pump
Flicker noise
Phase-locked loop
Power supply noise
Supply regulation
Voltage-controlled oscillator

ASJC Scopus subject areas

Electrical and Electronic Engineering

Online availability

10.1109/JSSC.2006.884194

Library availability

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title = "A 0.5-GHz to 2.5-GHz PLL with fully differential supply regulated tuning",

abstract = "This paper describes a wide-range clock generation phase-locked loop (PLL) incorporating several features that make it suitable for integration in highly scaled processes. A fully differential supply regulated tuning scheme is used to combat power supply noise. The charge pump uses a resistor rather than an active current source to define the pumping current in order to reduce the charge pump flicker noise. Fabricated in a 0.18-μm CMOS process, the PLL occupies 0.15 mm 2 die area and achieves a frequency range of 0.5 to 2.5 GHz. When operating at 2.4 GHz, the power consumption is 14 mA from a 1.8-V supply while the jitter is 2.36 ps rms.",

keywords = "Charge pump, Flicker noise, Phase-locked loop, Power supply noise, Supply regulation, Voltage-controlled oscillator",

author = "Merrick Brownlee and Hanumolu, {Pavan Kumar} and Kartikeya Mayaram and Moon, {Un Ku}",

note = "Funding Information: Manuscript received April 13, 2006; revised July 20, 2006. This work was supported by the Semiconductor Research Corporation (SRC) under Contract 2003-HJ-1076, and partly by Intel. The authors are with the School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR 97331 USA (e-mail: [email protected]). Digital Object Identifier 10.1109/JSSC.2006.884194",

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doi = "10.1109/JSSC.2006.884194",

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AU - Brownlee, Merrick

AU - Hanumolu, Pavan Kumar

AU - Mayaram, Kartikeya

AU - Moon, Un Ku

N1 - Funding Information: Manuscript received April 13, 2006; revised July 20, 2006. This work was supported by the Semiconductor Research Corporation (SRC) under Contract 2003-HJ-1076, and partly by Intel. The authors are with the School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR 97331 USA (e-mail: [email protected]). Digital Object Identifier 10.1109/JSSC.2006.884194

PY - 2006/12

Y1 - 2006/12

N2 - This paper describes a wide-range clock generation phase-locked loop (PLL) incorporating several features that make it suitable for integration in highly scaled processes. A fully differential supply regulated tuning scheme is used to combat power supply noise. The charge pump uses a resistor rather than an active current source to define the pumping current in order to reduce the charge pump flicker noise. Fabricated in a 0.18-μm CMOS process, the PLL occupies 0.15 mm 2 die area and achieves a frequency range of 0.5 to 2.5 GHz. When operating at 2.4 GHz, the power consumption is 14 mA from a 1.8-V supply while the jitter is 2.36 ps rms.

AB - This paper describes a wide-range clock generation phase-locked loop (PLL) incorporating several features that make it suitable for integration in highly scaled processes. A fully differential supply regulated tuning scheme is used to combat power supply noise. The charge pump uses a resistor rather than an active current source to define the pumping current in order to reduce the charge pump flicker noise. Fabricated in a 0.18-μm CMOS process, the PLL occupies 0.15 mm 2 die area and achieves a frequency range of 0.5 to 2.5 GHz. When operating at 2.4 GHz, the power consumption is 14 mA from a 1.8-V supply while the jitter is 2.36 ps rms.

KW - Charge pump

KW - Flicker noise

KW - Phase-locked loop

KW - Power supply noise

KW - Supply regulation

KW - Voltage-controlled oscillator

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A 0.5-GHz to 2.5-GHz PLL with fully differential supply regulated tuning

Abstract

Keywords

ASJC Scopus subject areas

Online availability

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