A 0.5-GHz to 2.5-GHz PLL with fully differential supply regulated tuning

Merrick Brownlee, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un Ku Moon

Research output: Contribution to journalArticlepeer-review


This paper describes a wide-range clock generation phase-locked loop (PLL) incorporating several features that make it suitable for integration in highly scaled processes. A fully differential supply regulated tuning scheme is used to combat power supply noise. The charge pump uses a resistor rather than an active current source to define the pumping current in order to reduce the charge pump flicker noise. Fabricated in a 0.18-μm CMOS process, the PLL occupies 0.15 mm 2 die area and achieves a frequency range of 0.5 to 2.5 GHz. When operating at 2.4 GHz, the power consumption is 14 mA from a 1.8-V supply while the jitter is 2.36 ps rms.

Original languageEnglish (US)
Pages (from-to)2720-2727
Number of pages8
JournalIEEE Journal of Solid-State Circuits
Issue number12
StatePublished - Dec 2006
Externally publishedYes


  • Charge pump
  • Flicker noise
  • Phase-locked loop
  • Power supply noise
  • Supply regulation
  • Voltage-controlled oscillator

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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