A 0.45-to-0.7V 1-to-6Gb/S 0.29-to-0.58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS

Woo Seok Choi, Guanghua Shu, Mrunmay Talegaonkar, Yubo Liu, Da Wei, Luca Benini, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Supply voltage (VDD) scaling offers a means to greatly reduce power in serial link transceivers. Ideally, power efficiency at a given data rate can be improved by reducing VDD while increasing the number of multiplexed circuits operating in parallel at lower clock frequencies [1]. Though increasing the amount of parallelism is desirable to scale VDD, in practice, it is limited by two main factors. First, increased sensitivity to device variations (threshold voltage/dimension mismatch) at lower VDD makes it extremely challenging to generate equally spaced multi-phase clocks needed in multiplexed transmitter and receiver. Phase calibration methods can correct phase-spacing errors [2,3], but their effectiveness at lower VDD is limited as the calibration circuits themselves become sensitive to device variations. Second, as oscillator output swing reduces with VDD, its phase noise degrades, making low-noise clock generation difficult to implement with low power dissipation. Phase noise can be suppressed by embedding the oscillator in a wide bandwidth analog phase-locked loop (APLL), but conventional charge-pump-based APLLs are difficult to design at low supply voltages (VDD <0.5V). Digital PLLs (DPLLs) can operate at low VDD, but they suffer from conflicting noise bandwidth tradeoffs, which prevent increasing the bandwidth to suppress oscillator phase noise adequately. In this paper, we present a phase-calibration method that enables the operation of a source-synchronous transceiver down to VDD of 0.45V. The energy efficiency and data-rate of the prototype transceiver scale from 0.29 to 0.58pJ/b and 1.3Gb/s to 6Gb/s, respectively, as VDD is varied from 0.45 to 0.7V.

Original languageEnglish (US)
Title of host publication2015 IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages66-67
Number of pages2
ISBN (Electronic)9781479962235
DOIs
StatePublished - Mar 17 2015
Event2015 62nd IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers - San Francisco, United States
Duration: Feb 22 2015Feb 26 2015

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume58
ISSN (Print)0193-6530

Other

Other2015 62nd IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers
CountryUnited States
CitySan Francisco
Period2/22/152/26/15

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'A 0.45-to-0.7V 1-to-6Gb/S 0.29-to-0.58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS'. Together they form a unique fingerprint.

  • Cite this

    Choi, W. S., Shu, G., Talegaonkar, M., Liu, Y., Wei, D., Benini, L., & Hanumolu, P. K. (2015). A 0.45-to-0.7V 1-to-6Gb/S 0.29-to-0.58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS. In 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers (pp. 66-67). [7062928] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 58). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2015.7062928