TY - JOUR
T1 - A 0.45-0.7 v 1-6 Gb/s 0.29-0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation
AU - Choi, Woo Seok
AU - Shu, Guanghua
AU - Talegaonkar, Mrunmay
AU - Liu, Yubo
AU - Wei, Da
AU - Benini, Luca
AU - Hanumolu, Pavan Kumar
N1 - Funding Information:
Manuscript received July 4, 2017; revised October 12, 2017 and December 5, 2017; accepted December 13, 2017. Date of publication January 17, 2018; date of current version February 21, 2018. This paper was approved by Associate Editor Woogeun Rhee. This work was supported in part by Analog Devices. (Corresponding author: Woo-Seok Choi.) W.-S. Choi, D. Wei, and P. K. Hanumolu are with the Department of Electrical and Computer Engineering, University of Illinois at Urbana– Champaign, Urbana, IL 61801 USA (e-mail: wchoi33@illinois.edu). G. Shu is with Oracle Labs, Belmont, CA 94002 USA. M. Talegaonkar is with Inphi Corporation, Irvine, CA 92618 USA. Y. Liu is with Qualcomm, San Diego, CA 92130 USA. L. Benini is with ETH Zurich, 8092 Zürich, Switzerland. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSSC.2017.2786716
Publisher Copyright:
© 1966-2012 IEEE.
PY - 2018/3
Y1 - 2018/3
N2 - A low-power source-synchronous multi-Gb/s transceiver is presented. Supply voltage is aggressively scaled to reduce power, and the speed penalty resulting from low-voltage operation is overcome by multiplexing transmitter/receiver synchronized by low-rate multi-phase clocks. Phase spacing errors incurred by device mismatches are corrected using a self-calibration scheme. The proposed phase calibration method uses a single digital DLL to calibrate all the phases, which makes it insensitive to offsets in the calibrating DLL. Fabricated in a 65-nm CMOS process, energy efficiency and data rate of the prototype transceiver vary from 0.29 to 0.58 pJ/bit and 1 to 6 Gb/s, respectively, as the supply voltage changes from 0.45 to 0.7 V.
AB - A low-power source-synchronous multi-Gb/s transceiver is presented. Supply voltage is aggressively scaled to reduce power, and the speed penalty resulting from low-voltage operation is overcome by multiplexing transmitter/receiver synchronized by low-rate multi-phase clocks. Phase spacing errors incurred by device mismatches are corrected using a self-calibration scheme. The proposed phase calibration method uses a single digital DLL to calibrate all the phases, which makes it insensitive to offsets in the calibrating DLL. Fabricated in a 65-nm CMOS process, energy efficiency and data rate of the prototype transceiver vary from 0.29 to 0.58 pJ/bit and 1 to 6 Gb/s, respectively, as the supply voltage changes from 0.45 to 0.7 V.
KW - Low-power I/O
KW - multi-phase calibration
KW - near-threshold-voltage circuit design
KW - near-threshold-voltage phase-locked loop (PLL)
KW - source-synchronous transceiver
UR - http://www.scopus.com/inward/record.url?scp=85041674144&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85041674144&partnerID=8YFLogxK
U2 - 10.1109/JSSC.2017.2786716
DO - 10.1109/JSSC.2017.2786716
M3 - Article
AN - SCOPUS:85041674144
SN - 0018-9200
VL - 53
SP - 884
EP - 895
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 3
ER -