Keyphrases
All-digital Phase-locked Loop (ADPLL)
100%
Analog PLL
33%
Area Saving
16%
Background Calibration
100%
Bandwidth Limitation
16%
Calibration Scheme
16%
Charge Pump
33%
Deterministic Test
16%
Digital Loop Filter
16%
Digital Nature
16%
Digital Phase-locked Loop
100%
Digital Systems
16%
Filter Capacitor
16%
Foreground Calibration
16%
Frequency Variation
16%
High Performance
16%
High-resolution TDC
16%
Highly Digital
16%
Highly Sensitive
16%
Jitter
16%
Jitter Performance
16%
Locking Behavior
16%
Long Loops
16%
Loop Filter
16%
Low Noise Oscillator
16%
Low Voltage
16%
Low-dropout Regulator
16%
Oscillator Phase Noise
16%
Output Frequency
16%
Process Variation
33%
Quantization Error
16%
Reconfiguration
16%
Ring Oscillator
16%
Signal Base
16%
Supply Noise
50%
Supply Noise Cancellation
100%
Temperature Variation
16%
Voltage Frequency
16%
Voltage Headroom
16%
Voltage Variation
16%
Engineering
Bandwidth Requirement
11%
Charge Pump
22%
Digital System
11%
Filter Capacitor
11%
High Resolution
11%
Loop Filter
22%
Loop Response
11%
Noise Cancellation
100%
Open Loop
11%
Output Frequency
11%
Phase Locked Loop
100%
Phase Noise
11%
Process Variation
22%
Quantisation Error
11%
Supply Voltage
11%
Test Signal
11%