A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration

Amr Elshazly, Rajesh Inti, Wenjing Yin, Brian Young, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Digital phase-locked loops (DPLLs) have recently emerged as a viable alternative to classical charge-pump analog PLLs [1-4]. By obviating the need for a large loop filter capacitor and a high-performance charge pump, DPLLs offer area savings and easier scalability to newer processes. The ability to reconfigure the digital loop filter dynamically offers flexibility in setting the loop response and helps to optimize the locking behavior of the DPLL [1]. However, conflicting bandwidth requirements to simultaneously suppress TDC quantization error and oscillator phase noise mandate either a high-resolution TDC or a low-noise oscillator to minimize jitter [2]. Further, much like in an analog PLL, the ring oscillator is susceptible to supply noise, which especially limits the jitter performance of a DPLL integrated into a large digital system. A low-dropout regulator is commonly used to shield the DCO from supply noise at the expense of additional area, power, and voltage headroom [3]. Alternatively, an open-loop supply-noise cancellation scheme can operate at a lower supply voltage, but its accuracy is highly sensitive to process variations [5]. Analog foreground calibration compensates for process variation but is susceptible to voltage, temperature, and frequency variations [6]. In this paper, we present a deterministic test-signal-based background calibration scheme that leverages the highly digital nature of the DPLL to adaptively cancel the supply noise in the DCO. The prototype DPLL achieves nearly perfect supply-noise cancellation over an output frequency range of 0.4 to 3GHz while consuming 2.65mW at 1.5GHz.

Original languageEnglish (US)
Title of host publication2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011
Pages92-93
Number of pages2
DOIs
StatePublished - May 12 2011
Externally publishedYes
Event2011 IEEE International Solid-State Circuits Conference, ISSCC 2011 - San Francisco, CA, United States
Duration: Feb 20 2011Feb 24 2011

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)0193-6530

Other

Other2011 IEEE International Solid-State Circuits Conference, ISSCC 2011
CountryUnited States
CitySan Francisco, CA
Period2/20/112/24/11

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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  • Cite this

    Elshazly, A., Inti, R., Yin, W., Young, B., & Hanumolu, P. K. (2011). A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration. In 2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011 (pp. 92-93). [5746233] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). https://doi.org/10.1109/ISSCC.2011.5746233