TY - GEN
T1 - A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration
AU - Elshazly, Amr
AU - Inti, Rajesh
AU - Yin, Wenjing
AU - Young, Brian
AU - Hanumolu, Pavan Kumar
PY - 2011
Y1 - 2011
N2 - Digital phase-locked loops (DPLLs) have recently emerged as a viable alternative to classical charge-pump analog PLLs [1-4]. By obviating the need for a large loop filter capacitor and a high-performance charge pump, DPLLs offer area savings and easier scalability to newer processes. The ability to reconfigure the digital loop filter dynamically offers flexibility in setting the loop response and helps to optimize the locking behavior of the DPLL [1]. However, conflicting bandwidth requirements to simultaneously suppress TDC quantization error and oscillator phase noise mandate either a high-resolution TDC or a low-noise oscillator to minimize jitter [2]. Further, much like in an analog PLL, the ring oscillator is susceptible to supply noise, which especially limits the jitter performance of a DPLL integrated into a large digital system. A low-dropout regulator is commonly used to shield the DCO from supply noise at the expense of additional area, power, and voltage headroom [3]. Alternatively, an open-loop supply-noise cancellation scheme can operate at a lower supply voltage, but its accuracy is highly sensitive to process variations [5]. Analog foreground calibration compensates for process variation but is susceptible to voltage, temperature, and frequency variations [6]. In this paper, we present a deterministic test-signal-based background calibration scheme that leverages the highly digital nature of the DPLL to adaptively cancel the supply noise in the DCO. The prototype DPLL achieves nearly perfect supply-noise cancellation over an output frequency range of 0.4 to 3GHz while consuming 2.65mW at 1.5GHz.
AB - Digital phase-locked loops (DPLLs) have recently emerged as a viable alternative to classical charge-pump analog PLLs [1-4]. By obviating the need for a large loop filter capacitor and a high-performance charge pump, DPLLs offer area savings and easier scalability to newer processes. The ability to reconfigure the digital loop filter dynamically offers flexibility in setting the loop response and helps to optimize the locking behavior of the DPLL [1]. However, conflicting bandwidth requirements to simultaneously suppress TDC quantization error and oscillator phase noise mandate either a high-resolution TDC or a low-noise oscillator to minimize jitter [2]. Further, much like in an analog PLL, the ring oscillator is susceptible to supply noise, which especially limits the jitter performance of a DPLL integrated into a large digital system. A low-dropout regulator is commonly used to shield the DCO from supply noise at the expense of additional area, power, and voltage headroom [3]. Alternatively, an open-loop supply-noise cancellation scheme can operate at a lower supply voltage, but its accuracy is highly sensitive to process variations [5]. Analog foreground calibration compensates for process variation but is susceptible to voltage, temperature, and frequency variations [6]. In this paper, we present a deterministic test-signal-based background calibration scheme that leverages the highly digital nature of the DPLL to adaptively cancel the supply noise in the DCO. The prototype DPLL achieves nearly perfect supply-noise cancellation over an output frequency range of 0.4 to 3GHz while consuming 2.65mW at 1.5GHz.
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U2 - 10.1109/ISSCC.2011.5746233
DO - 10.1109/ISSCC.2011.5746233
M3 - Conference contribution
AN - SCOPUS:79955739815
SN - 9781612843001
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 92
EP - 93
BT - 2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2011 IEEE International Solid-State Circuits Conference, ISSCC 2011
Y2 - 20 February 2011 through 24 February 2011
ER -