A 0.13μm 6Ghz 256×32b leakage-tolerant register file

R. Krishnamurthy, A. Alvandpour, G. Balamurugan, N. Shanbhag, K. Soumyanath, S. Borkar

Research output: Contribution to conferencePaper

Abstract

The description of a 0.13μm 6GHz 256×32b leakage-tolerant register file was presented. For improved leakage and noise tolerance, a pseudo-static local bitline (LBL) scheme that enabled 16 cells/bitline with all low-Vt transistors was proposed. A pseudo-static leakage tolerant scheme was used by the local bitline to achieve 36% higher DC noise robustness and 8% faster read performance compared to dual-Vt scheme optimized for high-performance.

Original languageEnglish (US)
Pages25-26
Number of pages2
StatePublished - Jan 1 2001
Externally publishedYes
Event2001 VLSI Circuits Symposium - Kyoto, Japan
Duration: Jun 14 2001Jun 16 2001

Other

Other2001 VLSI Circuits Symposium
CountryJapan
CityKyoto
Period6/14/016/16/01

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Krishnamurthy, R., Alvandpour, A., Balamurugan, G., Shanbhag, N., Soumyanath, K., & Borkar, S. (2001). A 0.13μm 6Ghz 256×32b leakage-tolerant register file. 25-26. Paper presented at 2001 VLSI Circuits Symposium, Kyoto, Japan.