A 0.016 mm2 0.26-μ W/MHz 60-240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS

Junheng Zhu, Woo Seok Choi, Pavan Kumar Hanumolu

Research output: Contribution to journalArticle

Abstract

Ultra-low-power systems, such as wearables and Internet-of-Things (IoT), require power- and volume-efficient micro-controller units (MCUs) capable of operating across a wide range of frequencies under extreme power constraints. This paper presents the techniques to implement clock generators that cater to the needs of such MCUs and other similar ultra-low-power applications. RC relaxation oscillators (RCOs) are shown to achieve excellent frequency stability when generating clocks in kilohertz to megahertz range but are not very power efficient (5 μW/MHz). Their power efficiency further degrades at higher frequencies because of additional power needed to compensate for the impact of temperature-dependent comparator's delay on frequency stability. On the other hand, ring oscillators (ROs) can generate higher frequency and lower noise clocks more power efficiently but exhibit very poor voltage and temperature sensitivity. In view of these complementary tradeoffs offered by RC oscillator and RO, this paper seeks to combine their advantages by using a phase-locked loop (PLL) to multiply the frequency of an RC oscillator using an RO. A new type-II digital PLL (DPLL) that uses a delay-modulating clock buffer to implement the proportional control and a low-area digital-to-analog converter to implement the digitally controlled oscillator is presented. Fabricated in the 65 nm CMOS process, the prototype PLL generates 50-300 MHz output frequencies from a reference clock in the range of 0.5-5 MHz. The DPLL occupies an active area of 125 μm × 125 μm and achieves ±0.33% period jitter while consuming 63.5 μW at an output frequency of 240 MHz. This translates to an excellent power efficiency of 0.26 μW/MHz at 0.8-V supply voltage.

Original languageEnglish (US)
Article number8723106
Pages (from-to)2186-2194
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Volume54
Issue number8
DOIs
StatePublished - Aug 1 2019

Fingerprint

Phase locked loops
Clocks
Frequency stability
Relaxation oscillators
Controllers
Electric potential
Digital to analog conversion
Jitter
Temperature

Keywords

  • digital PLL (DPLL)
  • digitally controlled ring oscillator (DCRO)
  • integer-N
  • period jitter
  • Phase-locked loops (PLLs)
  • RC relaxation oscillator (RCO)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

A 0.016 mm2 0.26-μ W/MHz 60-240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS. / Zhu, Junheng; Choi, Woo Seok; Hanumolu, Pavan Kumar.

In: IEEE Journal of Solid-State Circuits, Vol. 54, No. 8, 8723106, 01.08.2019, p. 2186-2194.

Research output: Contribution to journalArticle

@article{9f0ecff7efa5481a96997803db685e5e,
title = "A 0.016 mm2 0.26-μ W/MHz 60-240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS",
abstract = "Ultra-low-power systems, such as wearables and Internet-of-Things (IoT), require power- and volume-efficient micro-controller units (MCUs) capable of operating across a wide range of frequencies under extreme power constraints. This paper presents the techniques to implement clock generators that cater to the needs of such MCUs and other similar ultra-low-power applications. RC relaxation oscillators (RCOs) are shown to achieve excellent frequency stability when generating clocks in kilohertz to megahertz range but are not very power efficient (5 μW/MHz). Their power efficiency further degrades at higher frequencies because of additional power needed to compensate for the impact of temperature-dependent comparator's delay on frequency stability. On the other hand, ring oscillators (ROs) can generate higher frequency and lower noise clocks more power efficiently but exhibit very poor voltage and temperature sensitivity. In view of these complementary tradeoffs offered by RC oscillator and RO, this paper seeks to combine their advantages by using a phase-locked loop (PLL) to multiply the frequency of an RC oscillator using an RO. A new type-II digital PLL (DPLL) that uses a delay-modulating clock buffer to implement the proportional control and a low-area digital-to-analog converter to implement the digitally controlled oscillator is presented. Fabricated in the 65 nm CMOS process, the prototype PLL generates 50-300 MHz output frequencies from a reference clock in the range of 0.5-5 MHz. The DPLL occupies an active area of 125 μm × 125 μm and achieves ±0.33{\%} period jitter while consuming 63.5 μW at an output frequency of 240 MHz. This translates to an excellent power efficiency of 0.26 μW/MHz at 0.8-V supply voltage.",
keywords = "digital PLL (DPLL), digitally controlled ring oscillator (DCRO), integer-N, period jitter, Phase-locked loops (PLLs), RC relaxation oscillator (RCO)",
author = "Junheng Zhu and Choi, {Woo Seok} and Hanumolu, {Pavan Kumar}",
year = "2019",
month = "8",
day = "1",
doi = "10.1109/JSSC.2019.2915021",
language = "English (US)",
volume = "54",
pages = "2186--2194",
journal = "IEEE Journal of Solid-State Circuits",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "8",

}

TY - JOUR

T1 - A 0.016 mm2 0.26-μ W/MHz 60-240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS

AU - Zhu, Junheng

AU - Choi, Woo Seok

AU - Hanumolu, Pavan Kumar

PY - 2019/8/1

Y1 - 2019/8/1

N2 - Ultra-low-power systems, such as wearables and Internet-of-Things (IoT), require power- and volume-efficient micro-controller units (MCUs) capable of operating across a wide range of frequencies under extreme power constraints. This paper presents the techniques to implement clock generators that cater to the needs of such MCUs and other similar ultra-low-power applications. RC relaxation oscillators (RCOs) are shown to achieve excellent frequency stability when generating clocks in kilohertz to megahertz range but are not very power efficient (5 μW/MHz). Their power efficiency further degrades at higher frequencies because of additional power needed to compensate for the impact of temperature-dependent comparator's delay on frequency stability. On the other hand, ring oscillators (ROs) can generate higher frequency and lower noise clocks more power efficiently but exhibit very poor voltage and temperature sensitivity. In view of these complementary tradeoffs offered by RC oscillator and RO, this paper seeks to combine their advantages by using a phase-locked loop (PLL) to multiply the frequency of an RC oscillator using an RO. A new type-II digital PLL (DPLL) that uses a delay-modulating clock buffer to implement the proportional control and a low-area digital-to-analog converter to implement the digitally controlled oscillator is presented. Fabricated in the 65 nm CMOS process, the prototype PLL generates 50-300 MHz output frequencies from a reference clock in the range of 0.5-5 MHz. The DPLL occupies an active area of 125 μm × 125 μm and achieves ±0.33% period jitter while consuming 63.5 μW at an output frequency of 240 MHz. This translates to an excellent power efficiency of 0.26 μW/MHz at 0.8-V supply voltage.

AB - Ultra-low-power systems, such as wearables and Internet-of-Things (IoT), require power- and volume-efficient micro-controller units (MCUs) capable of operating across a wide range of frequencies under extreme power constraints. This paper presents the techniques to implement clock generators that cater to the needs of such MCUs and other similar ultra-low-power applications. RC relaxation oscillators (RCOs) are shown to achieve excellent frequency stability when generating clocks in kilohertz to megahertz range but are not very power efficient (5 μW/MHz). Their power efficiency further degrades at higher frequencies because of additional power needed to compensate for the impact of temperature-dependent comparator's delay on frequency stability. On the other hand, ring oscillators (ROs) can generate higher frequency and lower noise clocks more power efficiently but exhibit very poor voltage and temperature sensitivity. In view of these complementary tradeoffs offered by RC oscillator and RO, this paper seeks to combine their advantages by using a phase-locked loop (PLL) to multiply the frequency of an RC oscillator using an RO. A new type-II digital PLL (DPLL) that uses a delay-modulating clock buffer to implement the proportional control and a low-area digital-to-analog converter to implement the digitally controlled oscillator is presented. Fabricated in the 65 nm CMOS process, the prototype PLL generates 50-300 MHz output frequencies from a reference clock in the range of 0.5-5 MHz. The DPLL occupies an active area of 125 μm × 125 μm and achieves ±0.33% period jitter while consuming 63.5 μW at an output frequency of 240 MHz. This translates to an excellent power efficiency of 0.26 μW/MHz at 0.8-V supply voltage.

KW - digital PLL (DPLL)

KW - digitally controlled ring oscillator (DCRO)

KW - integer-N

KW - period jitter

KW - Phase-locked loops (PLLs)

KW - RC relaxation oscillator (RCO)

UR - http://www.scopus.com/inward/record.url?scp=85069872812&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85069872812&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2019.2915021

DO - 10.1109/JSSC.2019.2915021

M3 - Article

VL - 54

SP - 2186

EP - 2194

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 8

M1 - 8723106

ER -