A 0.0021mm2 1.82mW 2.2GHz PLL using time-based integral control in 65nm CMOS

Junheng Zhu, Romesh Kumar Nandwana, Guanghua Shu, Ahmed Elkholy, Seong Joong Kim, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Phase-locked loops (PLLs) are de-facto clock generators in analog, digital, RF, and embedded systems to generate a high frequency output clock from a low frequency reference clock. Modern systems-on-chip (SoCs) require many such PLLs that cater to multi-core processors, memories, IO interfaces and power management. A ring-oscillator-based analog charge-pump PLL offers a flexible and power-efficient way to implement such clock multipliers. However, frequency compensation of analog PLLs requires a large loop filter capacitor that occupies significant area. The area penalty is further exacerbated in deep sub-micron CMOS processes due to increasing oscillator gain and gate leakage. For example, a 2GHz PLL in 65nm CMOS requires a 90pF capacitor (R=1kω) to achieve 10MHz bandwidth and 70° phase margin. Assuming a capacitor density of 1fF/μm2, a 90pF capacitor occupies an area of 0.09mm2. Digital PLLs (DPLLs) offer an attractive means to eliminate the loop-filter capacitor [1, 2]. However, quantization error added by its loop components degrades the performance in multiple ways. First, it makes the DPLL loop inherently non-linear causing the steady state to be a bounded limit cycle, which manifests as deterministic jitter (DJ) at the PLL output. Second, it introduces conflicting noise bandwidth requirements, which makes it difficult to achieve low jitter in a power efficient manner. For instance, suppressing TDC quantization error by reducing PLL bandwidth increases the DCO phase noise contribution. As a result, DCO power must be increased to lower its noise contribution. This is especially problematic in ring-oscillator-based DPLLs. Finally, a high-resolution digital-to-analog converter (DAC) needed to interface the DLF output to the ring oscillator typically occupies large area and negates some of the area benefits of DPLLs [1, 2]. In view of these drawbacks, we present a PLL architecture that combines the advantages of analog (no quantization error) and digital PLLs (small area and scalability) by using a time-based integral path. The prototype PLL requires neither a high resolution DAC nor a capacitor and fits in 40μm×52μm (0.0021mm2) active area. It achieves 3.8psrms integrated jitter at 2.2GHz and consumes 1.82mW power.

Original languageEnglish (US)
Title of host publication2016 IEEE International Solid-State Circuits Conference, ISSCC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages338-340
Number of pages3
ISBN (Electronic)9781467394666
DOIs
StatePublished - Feb 23 2016
Event63rd IEEE International Solid-State Circuits Conference, ISSCC 2016 - San Francisco, United States
Duration: Jan 31 2016Feb 4 2016

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume59
ISSN (Print)0193-6530

Other

Other63rd IEEE International Solid-State Circuits Conference, ISSCC 2016
CountryUnited States
CitySan Francisco
Period1/31/162/4/16

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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