8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS

Guanghua Shu, Woo Seok Choi, Saurabh Saxena, Tejasvi Anand, Amr Elshazly, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Continuous-rate clock-and-data recovery (CDR) circuits with automatic frequency acquisition offer flexibility in both optical and electrical communication networks, and minimize cost with a single-chip multi-standard solution. The two major challenges in the design of such a CDR are: (a) extracting the bit-rate from the incoming random data stream, and (b) designing a wide-tuning-range low-noise oscillator. Among all available frequency detectors (FDs), the stochastic divider-based approach has the widest frequency acquisition range and is well suited for sub-rate CDRs [1]. However, its accuracy strongly depends on input transition density (0 ≤ ρ ≤ 1), with any deviation of ρ from 0.5 (50% transition density) causing 2×(ρ-0.5)×106 ppm of frequency error. In this paper, we present an automatic frequency-acquisition scheme that has unlimited range and is immune to variations in transition density. Implemented using a conventional bang-bang phase detector (BBPD), it requires minimum additional hardware and is applicable to sub-rate CDRs as well. Instead of using multiple LC oscillators that are carefully designed to cover a wide frequency range [2,3], a ring-oscillator-based fractional-N PLL is used as a digitally controlled oscillator (DCO) to achieve both wide range and low noise, and to decouple the tradeoff between jitter transfer (JTRAN) bandwidth and ring-oscillator-noise suppression.

Original languageEnglish (US)
Title of host publication2014 IEEE International Solid-State Circuits Conference, ISSCC 2014 - Digest of Technical Papers
Pages150-151
Number of pages2
DOIs
StatePublished - Apr 14 2014
Event2014 61st IEEE International Solid-State Circuits Conference, ISSCC 2014 - San Francisco, CA, United States
Duration: Feb 9 2014Feb 13 2014

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume57
ISSN (Print)0193-6530

Other

Other2014 61st IEEE International Solid-State Circuits Conference, ISSCC 2014
CountryUnited States
CitySan Francisco, CA
Period2/9/142/13/14

Fingerprint

Spurious signal noise
Clocks
Clock and data recovery circuits (CDR circuits)
Detectors
Recovery
Phase locked loops
Jitter
Telecommunication networks
Tuning
Hardware
Bandwidth
Costs

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Shu, G., Choi, W. S., Saxena, S., Anand, T., Elshazly, A., & Hanumolu, P. K. (2014). 8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS. In 2014 IEEE International Solid-State Circuits Conference, ISSCC 2014 - Digest of Technical Papers (pp. 150-151). [6757377] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 57). https://doi.org/10.1109/ISSCC.2014.6757377

8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS. / Shu, Guanghua; Choi, Woo Seok; Saxena, Saurabh; Anand, Tejasvi; Elshazly, Amr; Hanumolu, Pavan Kumar.

2014 IEEE International Solid-State Circuits Conference, ISSCC 2014 - Digest of Technical Papers. 2014. p. 150-151 6757377 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 57).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Shu, G, Choi, WS, Saxena, S, Anand, T, Elshazly, A & Hanumolu, PK 2014, 8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS. in 2014 IEEE International Solid-State Circuits Conference, ISSCC 2014 - Digest of Technical Papers., 6757377, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 57, pp. 150-151, 2014 61st IEEE International Solid-State Circuits Conference, ISSCC 2014, San Francisco, CA, United States, 2/9/14. https://doi.org/10.1109/ISSCC.2014.6757377
Shu G, Choi WS, Saxena S, Anand T, Elshazly A, Hanumolu PK. 8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS. In 2014 IEEE International Solid-State Circuits Conference, ISSCC 2014 - Digest of Technical Papers. 2014. p. 150-151. 6757377. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). https://doi.org/10.1109/ISSCC.2014.6757377
Shu, Guanghua ; Choi, Woo Seok ; Saxena, Saurabh ; Anand, Tejasvi ; Elshazly, Amr ; Hanumolu, Pavan Kumar. / 8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS. 2014 IEEE International Solid-State Circuits Conference, ISSCC 2014 - Digest of Technical Papers. 2014. pp. 150-151 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).
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