Abstract
A source-synchronous I/O link with adaptive receiver-side equalization has been implemented in 0.13-μm bulk CMOS technology. The transceiver is optimized for small area (360 μm × 360μm) and low power (280 mW). The analog equalizer is implemented as an 8-way interleaved, 4-tap discrete-time linear filter. The equalization improved the data rate of a 102 cm backplane interconnect by 110%. On-die adaptive logic determines optimal receiver settings through comparator offset cancellation, data alignment of the transmitter and receiver, clock de-skew and setting filter coefficients for equalization. The noise-margin degradation due to statistical variation in converged coefficient values was less than 3%.
Original language | English (US) |
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Pages (from-to) | 80-87 |
Number of pages | 8 |
Journal | IEEE Journal of Solid-State Circuits |
Volume | 40 |
Issue number | 1 |
DOIs | |
State | Published - Jan 2005 |
Keywords
- Adaptive equalizers
- Analog equalization
- High-speed I/O
- Offset cancellation
- Transceivers
- Waveform capture
ASJC Scopus subject areas
- Electrical and Electronic Engineering