7.8 A 69.3fs Ring-Based Sampling-PLL Achieving 6.8GHz-14GHz and -54.4dBc Spurs under 50mV Supply Noise

Mahmoud A. Khalil, Mohamed Badr Younis, Ruhao Xia, Ahmed E. Abdelrahman, Tianyu Wang, Kyu Sang Park, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceedingConference contribution


A low-jitter multi-phase clock generator is pivotal in high-speed serial link transceivers. With data rates surpassing 100Gb/s, incorporating sub-rate operations becomes essential to overcome inherent bandwidth constraints. This, in turn, demands the generation of multiple sub-rate clock phases. However, the difficulty lies in producing these clock signals with minimal jitter, particularly at high frequencies (>10GHz). Contemporary clock generators with integrated jitter below 100fsrms primarily utilize LC oscillators [1]. However, LC-based phase-locked loops (PLLs) occupy considerable space, lack efficiency in generating multiple phases, and are vulnerable to electromagnetic coupling in multi-lane SerDes systems. In contrast, ring-oscillator (RO) based architectures offer a compact footprint and inherent suitability for multi-phase clock generation. As a result, there is a growing need for resilient RO-based PLLs that can achieve jitter levels comparable to those of LC-based alternatives. However, the performance of these PLLs is hindered by excessive noise inherent to the RO, a challenge further exacerbated by the requirement to function within noisy supply environments and across a wide temperature range. Prior investigations [2-4] have recognized this limitation and focused on widening the RO phase noise suppression bandwidth. To illustrate, an injection-locked PLL was employed to extend the bandwidth to approximately one-sixth of the reference frequency (FREF) in [2]. These techniques, while effective, necessitate intricate frequency-tracking loops that prove challenging to implement while aiming for low jitter across a wide frequency range. An alternate approach detailed in [4] accomplished 135fs jitter but relied on an FREF of 1.85GHz, yielding a modest 7GHz output. Recent trends have seen sampling PLLs emerge, lessening the noise concerns inherent to traditional PLLs [1]. Nevertheless, achieving <100fs jitter performance and >10GHz output using an RO remains elusive. Given these limitations, this paper presents an 8-phase sampling PLL that operates from 6.8GHz to 14GHz (2× higher output frequency compared to [4]) and achieves an integrated jitter of 69.3fs (one-third of the jitter reported in [2]), an in-band noise level of -131.4dBc, and a spur level below -54.4dBc under 50mVpp supply ripple.

Original languageEnglish (US)
Title of host publication2024 IEEE International Solid-State Circuits Conference, ISSCC 2024
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages3
ISBN (Electronic)9798350306200
StatePublished - 2024
Event2024 IEEE International Solid-State Circuits Conference, ISSCC 2024 - San Francisco, United States
Duration: Feb 18 2024Feb 22 2024

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)0193-6530


Conference2024 IEEE International Solid-State Circuits Conference, ISSCC 2024
Country/TerritoryUnited States
CitySan Francisco

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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