40 Gb/s VCSELs test data collection, analysis, and process problem identification

Junyi Qiu, Hsiao Lun Wang, Curtis Y.L. Wang, Xin Yu, Milton Feng

Research output: Contribution to conferencePaperpeer-review

Abstract

This paper reviews the on-wafer testing and subsequent data analysis procedures of 40 Gb/s oxide-confined VCSELs. Several key performance metrics are carefully defined and their measurement procedure explained. After data collection, a wafer-scale heat map is constructed to help to visualize device performance uniformity in terms of output power, threshold, and optical aperture diameter. Further data analysis reveals that the large variation of output power in this sample can be attributed to the VCSEL window quality, which is confirmed by reexamining the sample. Thus we have used VCSEL testing data analysis techniques to identify device processing issues, fully utilizing device testing as important quality assurance and information feedback step.

Original languageEnglish (US)
StatePublished - Jan 1 2017
Event2017 International Conference on Compound Semiconductor Manufacturing Technology, CS MANTECH 2017 - Indian Wells, United States
Duration: May 22 2017May 25 2017

Other

Other2017 International Conference on Compound Semiconductor Manufacturing Technology, CS MANTECH 2017
CountryUnited States
CityIndian Wells
Period5/22/175/25/17

Keywords

  • Data analysis
  • Testing
  • VCSEL

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of '40 Gb/s VCSELs test data collection, analysis, and process problem identification'. Together they form a unique fingerprint.

Cite this