32×16 CMOS smart pixel array for optical interconnects

Jongwoo Kim, Peter Guilfoyle, Richard Stone, John Hessenbruch, Kent D Choquette, Fouad Kiamilev

Research output: Contribution to journalArticlepeer-review


Free space optical interconnects can increase throughput capacities and eliminate much of the energy consumption required for `all electronic' systems. High speed optical interconnects can be achieved by integrating optoelectronic devices with conventional electronics. Smart pixel arrays have been developed which use optical interconnects. An individual smart pixel cell is composed of a vertical cavity surface emitting laser (VCSEL), a photodetector, an optical receiver, a laser driver, and digital logic circuitry. Oxide-confined VCSELs are being developed to operate at 850 nm with a threshold current of approximately 1 mA. Multiple quantum well (MQW) photodetectors are being fabricated from AlGaAs for use with the 850 nm VCSELs. The VCSELs and photodetectors are being integrated with complementary metal oxide semiconductor (CMOS) circuitry using flip-chip bonding. CMOS circuitry is being integrated with a 32×16 smart pixel array. The 512 smart pixels are serially linked. Thus, an entire data stream may be clocked through the chip and output electrically by the last pixel. Electrical testing is being performed on the CMOS smart pixel array. Using an on-chip pseudo random number generator, a digital data sequence was cycled through the chip verifying operation of the digital circuitry. Although, the prototype chip was fabricated in 1.2 μm technology, simulations have demonstrated that the array can operate at 1 Gb/s per pixel using 0.5 μm technology.

Original languageEnglish (US)
Pages (from-to)721-724
Number of pages4
JournalProceedings of SPIE - The International Society for Optical Engineering
StatePublished - 2000
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Condensed Matter Physics


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