3-D nFPGA: A reconfigurable architecture for 3-D CMOS/nanomaterial hybrid digital circuits

Chen Dong, Deming Chen, Sansiri Haruehanroengra, Wei Wang

Research output: Contribution to journalArticlepeer-review


In this paper, we introduce a novel reconfigurable architecture, named 3D field-programmable gate array (3D nFPGA), which utilizes 3D integration techniques and new nanoscale materials synergistically. The proposed architecture is based on CMOS nanohybrid techniques that incorporate nanomaterials such as carbon nanotube bundles and nanowire crossbars into CMOS fabrication process. This architecture also has built-in features for fault tolerance and heat alleviation. Using unique features of FPGAs and a novel 3D stacking method enabled by the application of nanomaterials, 3D nFPGA obtains a 4× footprint reduction comparing to the traditional CMOS-based 2D FPGAs. With a customized design automation flow, we evaluate the performance and power of 3D nFPGA driven by the 20 largest MCNC benchmarks. Results demonstrate that 3D nFPGA is able to provide a performance gain of 2.6 × with a small power overhead comparing to the traditional 2D FPGA architecture.

Original languageEnglish (US)
Pages (from-to)2489-2501
Number of pages13
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Issue number11 SPEC. ISS.
StatePublished - 2007


  • 3-D integration
  • Nanoelectronics
  • Nanotube
  • Nanowire
  • Performance
  • Reconfigurable logic

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture


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