25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM

Yong Hun Kim, Hyung Jin Kim, Jaemin Choi, Min Su Ahn, Dongkeon Lee, Seung Hyun Cho, Dong Yeon Park, Young Jae Park, Min Soo Jang, Yong Jun Kim, Jinyong Choi, Sung Woo Yoon, Jae Woo Jung, Jae Koo Park, Jae Woo Lee, Dae Hyun Kwon, Hyung Seok Cha, Si Hyeong Cho, Seong Hoon Kim, Jihwa YouKyoung Ho Kim, Dae Hyun Kim, Byung Cheol Kim, Young Kwan Kim, Jun Ho Kim, Seouk Kyu Choi, Chan Young Kim, Byong Wook Na, Hye In Choi, Reum Oh, Jeong Don Ihm, Seung Jun Bae, Nam Sung Kim, Jung Bae Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The demand for mobile DRAM has increased, with a requirement for high density, high data rates, and low-power consumption to support applications such as 5G communication, multiple cameras, and automotive. Thus, density has increased from 2Gb [1] to 16Gb [2] in LPDDR4 and LPDDR4X, but the maximum density for LPDDR5 is only 12Gb [3] due to the limited package size specification: such as a 496-ball FBGA. In this work, a mosaic architecture is introduced to increase the density to 16Gb, even in a limited package size. Additionally, the I/O performance is improved by shortening the length for the top metal, and a short-feedback sense amplifier (SA) with dedicated VREFs for a 1-tap DFE. The side effect of a mosaic architecture is the performance of the internal DRAM due to a 1.64× long bus line; however, this is mitigated by a fully-source-synchronous (FSS) bus scheme that is robust to PVT variation. In addition, to reduce the power consumption of the long bus line a low-level swing (LLS) scheme is used in low frequency mode. Furthermore, to enhance power efficiency and yield an adaptive-body-bias (ABB) scheme is introduced in a 3rd generation of a 10nm DRAM process.

Original languageEnglish (US)
Title of host publication2021 IEEE International Solid-State Circuits Conference, ISSCC 2021 - Digest of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages346-348
Number of pages3
ISBN (Electronic)9781728195490
DOIs
StatePublished - Feb 13 2021
Externally publishedYes
Event2021 IEEE International Solid-State Circuits Conference, ISSCC 2021 - San Francisco, United States
Duration: Feb 13 2021Feb 22 2021

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume64
ISSN (Print)0193-6530

Conference

Conference2021 IEEE International Solid-State Circuits Conference, ISSCC 2021
Country/TerritoryUnited States
CitySan Francisco
Period2/13/212/22/21

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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