Abstract
A high-speed, high-voltage polysilicon-emitter complementary bipolar IC process is described. Process features include >170 V NPN and PNP BVceo, dielectric isolation using a bonded wafer substrate and deep trenches, polysilicon resistors, polysilicon to metal capacitors, and a two-level metal back end.
Original language | English (US) |
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Title of host publication | Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting |
Editors | Anon |
Publisher | IEEE |
Pages | 183-186 |
Number of pages | 4 |
State | Published - 1997 |
Externally published | Yes |
Event | Proceedings of the 1997 Bipolar/BiCMOS Circuits and Technology Meeting - Minneapolis, MN, USA Duration: Sep 28 1997 → Sep 30 1997 |
Other
Other | Proceedings of the 1997 Bipolar/BiCMOS Circuits and Technology Meeting |
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City | Minneapolis, MN, USA |
Period | 9/28/97 → 9/30/97 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering