15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS

Modern systems-on-chips (SoCs) perform many diverse analog, digital, and mixed-signal functions. They contain a wide variety of modules such as multicore processors, memories, I/O interfaces, power management, and wireless transceivers. Each module has its own unique clock requirements to maximize the overall system performance. For example, dynamic frequency scaling (DFS) saves processor power, spread spectrum clocking (SSC) reduces electromagnetic interference (EMI), and rapid power cycling between idle and active states allows energy-proportional operation. A conventional analog integer-N phase-locked loop (PLL)-based clock generation unit (CGU) occupies large area, has a long lock time, and its output frequency resolution is limited by the reference clock frequency. While the digital fractional-N PLL-based CGU in [1] overcomes some of these drawbacks, it suffers from an intrinsic tradeoff between the time-to-digital converter (TDC)/fractional-divider quantization error and oscillator phase noise. As a result, it requires either a high-resolution TDC or a low-noise oscillator both of which incur power penalty. Further, narrow PLL bandwidth limits SSC modulation frequency and increases lock time making it unsuitable for energy-proportional operation. Open-loop frequency generation using direct-digital synthesis (DDS) overcomes the drawbacks of closed-loop PLLs but it consumes a significant amount of power [2]. This paper presents an all-digital CGU using open-loop fractional dividers. Unlike [1], the proposed CGU, using only one integer-N PLL and a single reference clock, can provide multiple low-jitter outputs over a wide frequency range with fine frequency resolution. It also has SSC capability with programmable modulation depth and achieves instantaneous frequency switching.