Shobha Vasudevan

20042019
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Research Output 2004 2019

  • 43 Conference contribution
  • 15 Article
  • 2 Conference article
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Article
2019

Assertion Ranking using RTL Source Code Analysis

Pal, D., Offenberger, S. & Vasudevan, S., Jan 1 2019, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Research output: Contribution to journalArticle

Directed graphs
2018
Restoration
Silicon
Scalability
Networks (circuits)
2017

A novel test compression algorithm for analog circuits to decrease production costs

Ahmadyan, S. N., Natarajan, S. & Vasudevan, S., Jun 1 2017, In : Integration, the VLSI Journal. 58, p. 538-548 11 p.

Research output: Contribution to journalArticle

Analog circuits
Operational amplifiers
Variable frequency oscillators
Transient analysis
Costs
2016

Automated Transient Input Stimuli Generation for Analog Circuits

Ahmadyan, S. N. & Vasudevan, S., May 1 2016, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 35, 5, p. 858-871 14 p., 7294671.

Research output: Contribution to journalArticle

Analog circuits
Scalability
Feedback
2014

Efficient statistical model checking of hardware circuits with multiple failure regions

Kumar, J. A., Ahmadyan, S. N. & Vasudevan, S., Jan 1 2014, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 33, 6, p. 945-958 14 p., 6816114.

Research output: Contribution to journalArticle

Model checking
Hardware
Networks (circuits)
Statistical Models
Static random access storage
Static analysis
Dynamic analysis
Explosions
Concretes
Surface mount technology
2013

Automatic generation of system level assertions from transaction level models

Liu, L. & Vasudevan, S., Oct 1 2013, In : Journal of Electronic Testing: Theory and Applications (JETTA). 29, 5, p. 669-684 16 p.

Research output: Contribution to journalArticle

Temporal logic
Dynamic mechanical analysis
Engines
Specifications
Controllers

Formal probabilistic timing verification in RTL

Kumar, J. A. & Vasudevan, S., May 1 2013, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 32, 5, p. 788-801 14 p., 6504532.

Research output: Contribution to journalArticle

Markov processes
Communication systems
Costs
Statistical Models

Mining hardware assertions with guidance from static analysis

Hertz, S., Sheridan, D. & Vasudevan, S., May 23 2013, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 32, 6, p. 952-965 14 p., 6516599.

Research output: Contribution to journalArticle

Static analysis
Data mining
Hardware
Engines
Supervised learning
2012

A technique for test coverage closure using goldmine

Liu, L., Sheridan, D., Tuohy, W. & Vasudevan, S., May 1 2012, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 31, 5, p. 790-803 14 p., 6186862.

Research output: Contribution to journalArticle

Decision trees
Engines
Binary decision diagrams
Learning algorithms
Data mining

Formal performance analysis for faulty MIMO hardware

Kumar, J. A. & Vasudevan, S., Jan 1 2012, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20, 10, p. 1914-1918 5 p., 6016225.

Research output: Contribution to journalArticle

Hardware
Model checking
Temporal logic
Large scale systems
Communication systems
2009

Dedicated rewriting: Automatic verification of low power transformations in Register Transfer Level

Viswanath, V., Vasudevan, S. & Abraham, J. A., Oct 1 2009, In : Journal of Low Power Electronics. 5, 3, p. 339-353 15 p.

Research output: Contribution to journalArticle

Hardware
Microprocessor chips
Computer hardware description languages
Networks (circuits)
System-on-chip
2008

Sequential equivalence checking between system level and RTL descriptions

Vasudevan, S., Viswanath, V., Abraham, J. A. & Tu, J., Dec 1 2008, In : Design Automation for Embedded Systems. 12, 4, p. 377-396 20 p.

Research output: Contribution to journalArticle

Computer hardware description languages
System-on-chip
2007

Automatic verification of arithmetic circuits in RTL using stepwise refinement of term rewriting systems

Vasudevan, S., Viswanath, V., Sumners, R. W. & Abraham, J. A., Oct 1 2007, In : IEEE Transactions on Computers. 56, 10, p. 1401-1414 14 p.

Research output: Contribution to journalArticle

Term Rewriting Systems
Arithmetic Circuits
Automatic Verification
Circuit Design
Refinement

Improved verification of hardware designs through antecedent conditioned slicing

Vasudevan, S., Emerson, E. A. & Abraham, J. A., Feb 1 2007, In : International Journal on Software Tools for Technology Transfer. 9, 1, p. 89-101 13 p.

Research output: Contribution to journalArticle

Hardware
Computer hardware description languages
Temporal logic
Specifications