Shobha Vasudevan

20042019
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Research Output 2004 2019

  • 43 Conference contribution
  • 15 Article
  • 2 Conference article
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Conference contribution
2019

A figure of merit for assertions in verification

Hertz, S., Pal, D., Offenberger, S. & Vasudevan, S., Jan 21 2019, ASP-DAC 2019 - 24th Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc., p. 675-680 6 p. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Silicon

Automated Generation and Selection of Interpretable Features for Enterprise Security

Duan, J., Zeng, Z., Oprea, A. & Vasudevan, S., Jan 22 2019, Proceedings - 2018 IEEE International Conference on Big Data, Big Data 2018. Song, Y., Liu, B., Lee, K., Abe, N., Pu, C., Qiao, M., Ahmed, N., Kossmann, D., Saltz, J., Tang, J., He, J., Liu, H. & Hu, X. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 1258-1265 8 p. 8621986. (Proceedings - 2018 IEEE International Conference on Big Data, Big Data 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Fourier analysis
Boolean functions
Clustering algorithms
Learning systems
Industry

Guilty As Charged: Computational Reliability Threats Posed by Electrostatic Discharge-induced Soft Errors

Feng, K., Vora, S., Jiang, R., Rosenbaum, E. & Vasudevan, S., May 14 2019, Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019. Institute of Electrical and Electronics Engineers Inc., p. 156-161 6 p. 8715149. (Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Soft Error
Electrostatic discharge
Electrostatics
Chip
Microcontroller
2018

Application level hardware tracing for scaling post-silicon debug

Pal, D., Sharma, A., Ray, S., De Paula, F. M. & Vasudevan, S., Jun 24 2018, Proceedings of the 55th Annual Design Automation Conference, DAC 2018. Institute of Electrical and Electronics Engineers Inc., Vol. Part F137710. a92

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Tracing
Silicon
Trace
Hardware
Debugging

Hardware and software combined detection of system-level ESD-induced soft failures

Vora, S., Jiang, R., Vijayaraj, P. M., Feng, K., Xiu, Y., Vasudevan, S. & Rosenbaum, E., Oct 25 2018, Electrical Overstress/Electrostatic Discharge Symposium Proceedings, EOS/ESD 2018. ESD Association, (Electrical Overstress/Electrostatic Discharge Symposium Proceedings; vol. 2018-September).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Microcontrollers
Computer hardware
Hardware
Data storage equipment
Electric potential
2017

Still a fight to get it right: Verification in the era of machine learning

Vasudevan, S., Nov 28 2017, 2017 IEEE International Conference on Rebooting Computing, ICRC 2017 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 1-8 8 p. (2017 IEEE International Conference on Rebooting Computing, ICRC 2017 - Proceedings; vol. 2017-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

machine learning
Learning systems
Hardware
hardware
Learning algorithms
2016

Application level investigation of system-level ESD-induced soft failures

Vora, S., Jiang, R., Vasudevan, S. & Rosenbaum, E., Oct 14 2016, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2016, EOS/ESD 2016. ESD Association, 7592565. (Electrical Overstress/Electrostatic Discharge Symposium Proceedings; vol. 2016-October).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Program processors
Hardware

Can't see the forest for the trees: State restoration's limitations in post-silicon trace signal selection

Ma, S., Pal, D., Jiang, R., Ray, S. & Vasudevan, S., Jan 5 2016, 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015. Institute of Electrical and Electronics Engineers Inc., p. 1-8 8 p. 7372542. (2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Restoration
Silicon

Duplex: Simultaneous parameter-performance exploration for optimizing analog circuits

Ahmadyan, S. N. & Vasudevan, S., Nov 7 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2016. Institute of Electrical and Electronics Engineers Inc., 2967026. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD; vol. 07-10-November-2016).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Analog circuits
Networks (circuits)
Phase locked loops
Scalability
Pumps

Every test makes a difference: Compressing analog tests to decrease production costs

Ahmadyan, S. N., Natarajan, S. & Vasudevan, S., Mar 7 2016, 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016. Institute of Electrical and Electronics Engineers Inc., p. 539-544 6 p. 7428067. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 25-28-January-2016).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Operational amplifiers
Variable frequency oscillators
Analog circuits
Transient analysis
Costs

Symptomatic Bug Localization for Functional Debug of Hardware Designs

Pal, D. & Vasudevan, S., Mar 16 2016, Proceedings - 29th International Conference on VLSI Design, VLSID 2016 - Held concurrently with 15th International Conference on Embedded Systems. IEEE Computer Society, p. 517-522 6 p. 7435006. (Proceedings of the IEEE International Conference on VLSI Design; vol. 2016-March).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
Silicon
2015

Fast eye diagram analysis for high-speed CMOS circuits

Ahmadyan, S. N., Gu, C., Natarajan, S., Chiprout, E. & Vasudevan, S., Apr 22 2015, Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015. Institute of Electrical and Electronics Engineers Inc., Vol. 2015-April. p. 1377-1382 6 p. 7092606

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Jitter
Topology
Networks (circuits)
Monte Carlo simulation

Packer classifier based on PE header information

Jin, Q., Duan, J., Vasudevan, S. & Bailey, M. D., Apr 21 2015, Proceedings of the 2015 Symposium and Bootcamp on the Science of Security, HotSoS 2015. Association for Computing Machinery, 2746213. (ACM International Conference Proceeding Series; vol. 21-22-April-2015).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Packers
Classifiers
Malware
2014

A coverage guided mining approach for automatic generation of succinct assertions

Sheridan, D., Liu, L., Kim, H. & Vasudevan, S., Mar 3 2014, Proceedings - 27th International Conference on VLSI Design, VLSID 2014; Held Concurrently with 13th International Conference on Embedded Systems Design. p. 68-73 6 p. 6733108. (Proceedings of the IEEE International Conference on VLSI Design).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Decision trees
Feedback
Hardware
Association rules
Learning systems

Code coverage of assertions using RTL source code analysis

Athavale, V., Ma, S., Hertz, S. & Vasudevan, S., Jan 1 2014, DAC 2014 - 51st Design Automation Conference, Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 2593108. (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Assertion
Coverage
Static analysis
Dynamic analysis
Scalability
2013

Diagnosing root causes of system level performance violations

Liu, L., Zhong, X., Chen, X. & Vasudevan, S., Dec 1 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2013 - Digest of Technical Papers. p. 295-302 8 p. 6691135. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Throughput

Generating concise assertions with complete coverage

Lin, C. H., Liu, L. & Vasudevan, S., May 30 2013, GLSVLSI 2013 - Proceedings of the ACM International Conference of the Great Lakes Symposium on VLSI. p. 185-190 6 p. (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ethernet
Scalability
Integrated circuit design
Formal verification

Reachability analysis of nonlinear analog circuits through iterative reachable set reduction

Ahmadyan, S. N. & Vasudevan, S., 2013, Proceedings - Design, Automation and Test in Europe, DATE 2013. p. 1436-1441 6 p. 6513739

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Analog circuits
Circuit oscillations
Trajectories
Acoustic waves
Data storage equipment

Runtime verification of nonlinear analog circuits using incremental time-augmented RRT algorithm

Ahmadyan, S. N., Kumar, J. A. & Vasudevan, S., Oct 21 2013, Proceedings - Design, Automation and Test in Europe, DATE 2013. p. 21-26 6 p. 6513465. (Proceedings -Design, Automation and Test in Europe, DATE).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Analog circuits
Specifications
Data storage equipment
Monitoring

Scaling RTL property checking using feasible path analysis and decomposition

Liu, L. & Vasudevan, S., May 30 2013, GLSVLSI 2013 - Proceedings of the ACM International Conference of the Great Lakes Symposium on VLSI. p. 173-178 6 p. (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Surface mount technology
Decomposition
Concretes

Using automatically generated invariants for regression testing and bug localization

Sagdeo, P., Ewalt, N., Pal, D. & Vasudevan, S., Dec 1 2013, 2013 28th IEEE/ACM International Conference on Automated Software Engineering, ASE 2013 - Proceedings. p. 634-639 6 p. 6693125. (2013 28th IEEE/ACM International Conference on Automated Software Engineering, ASE 2013 - Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Testing
Statistical methods
Engines
2012

Early prediction of NBTI effects using RTL source code analysis

Kumar, J. A., Butler, K. M., Kim, H. & Vasudevan, S., Jul 11 2012, Proceedings of the 49th Annual Design Automation Conference, DAC '12. p. 808-813 6 p. (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Degradation
Prediction
Estimate
Methodology
Model checking

Goal-oriented stimulus generation for analog circuits

Ahmadyan, S. N., Kumar, J. A. & Vasudevan, S., Jul 11 2012, Proceedings of the 49th Annual Design Automation Conference, DAC '12. p. 1018-1023 6 p. (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Analog Circuits
Analog circuits
Methodology
Networks (circuits)
Nonlinear Circuits

Using static analysis for coverage extraction from emulation/prototyping platforms

Athavale, V., Hertz, S., Jetly, D., Ganesan, V., Krysl, J. & Vasudevan, S., Nov 19 2012, CODES+ISSS'12 - Proceedings of the 10th ACM International Conference on Hardware/Software-Codesign and System Synthesis, Co-located with ESWEEK. p. 207-214 8 p. (CODES+ISSS'12 - Proceedings of the 10th ACM International Conference on Hardware/Software-Codesign and System Synthesis, Co-located with ESWEEK).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Static analysis
Hardware
Visibility
Statistics
Industry

Verifying dynamic power management schemes using statistical model checking

Kumar, J. A. & Vasudevan, S., Apr 26 2012, ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference. p. 579-584 6 p. 6165023. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Model checking
Statistical Models
Power management
Industry
2011

Automatic generation of assertions from system level design using data mining

Liu, L., Sheridan, D., Athavale, V. & Vasudevan, S., Sep 1 2011, 9th ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2011. p. 191-200 10 p. 5970526. (9th ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2011).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Assertion
Data mining
Data Mining
Transactions
Mining

Efficient validation input generation in RTL by hybridized source code analysis

Liu, L. & Vasudevan, S., May 31 2011, Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011. p. 1596-1601 6 p. 5763253. (Proceedings -Design, Automation and Test in Europe, DATE).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Flow graphs
Guards (shields)
Engines
Computer hardware description languages
Surface mount technology

PRECIS: Inferring invariants using program path guided clustering

Sagdeo, P., Athavale, V., Kowshik, S. & Vasudevan, S., Dec 1 2011, 2011 26th IEEE/ACM International Conference on Automated Software Engineering, ASE 2011, Proceedings. p. 532-535 4 p. 6100117. (2011 26th IEEE/ACM International Conference on Automated Software Engineering, ASE 2011, Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Linear regression

Scaling probabilistic timing verification of hardware using abstractions in design source code

Kumar, J. A., Liu, L. & Vasudevan, S., Dec 1 2011, 2011 Formal Methods in Computer-Aided Design, FMCAD 2011. p. 196-205 10 p. 6148897. (2011 Formal Methods in Computer-Aided Design, FMCAD 2011).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
Model checking
Markov processes
Fast Fourier transforms
Communication systems

Signature pattern covering via local greedy algorithm and Pattern Shrink

Kim, H., Im, S., Abdelzaher, T., Han, J., Sheridan, D. & Vasudevan, S., Dec 1 2011, Proceedings - 11th IEEE International Conference on Data Mining, ICDM 2011. p. 330-339 10 p. 6137237. (Proceedings - IEEE International Conference on Data Mining, ICDM).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Labels
Hardware

Towards coverage closure: Using GoldMine assertions for generating design validation stimulus

Liu, L., Sheridan, D., Tuohy, W. & Vasudevan, S., May 31 2011, Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2011. p. 173-178 6 p. 5763038. (Proceedings -Design, Automation and Test in Europe, DATE).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Decision trees
Engines
Learning algorithms
Data mining
Formal verification

Variation-conscious formal timing verification in RTL

Kumar, J. A. & Vasudevan, S., Mar 25 2011, Proceedings - 24th International Conference on VLSI Design, VLSI Design 2011, Held Jointly with 10th International Conference on Embedded Systems. p. 58-63 6 p. 5718778. (Proceedings of the IEEE International Conference on VLSI Design).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Model checking
Markov processes
Scalability
Networks (circuits)
Costs
2010

A scalable approach for throughput estimation of timing speculation designs

Athavale, V., Kumar, J. A. & Vasudevan, S., Sep 20 2010, 2010 IEEE International 53rd Midwest Symposium on Circuits and Systems, MWSCAS 2010. p. 1234-1237 4 p. 5548771. (Midwest Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Throughput
Networks (circuits)
Combinatorial circuits
Digital circuits
Scalability

Automatic compositional reasoning for probabilistic model checking of hardware designs

Kumar, J. A. & Vasudevan, S., Dec 2 2010, Proceedings - 7th International Conference on the Quantitative Evaluation of Systems, QEST 2010. p. 143-152 10 p. 5600395. (Proceedings - 7th International Conference on the Quantitative Evaluation of Systems, QEST 2010).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Model checking
Hardware
Adders
Bit error rate
Scalability

GoldMine: Automatic assertion generation using data mining and static analysis

Vasudevan, S., Sheridan, D., Patel, S. J., Tcheng, D., Tuohy, B. & Johnson, D., Jun 9 2010, DATE 10 - Design, Automation and Test in Europe. p. 626-629 4 p. 5457129. (Proceedings -Design, Automation and Test in Europe, DATE).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Static analysis
Data mining

Statistical guarantees of performance for MIMO designs

Kumar, J. A. & Vasudevan, S., Sep 20 2010, Proceedings of the 2010 IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2010. p. 467-476 10 p. 5544281. (Proceedings of the International Conference on Dependable Systems and Networks).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Model checking
Temporal logic
Explosions
Scalability
Systems analysis
2009

Dedicated rewriting: Automatic verification of low power transformations in RTL

Viswanath, V., Vasudevan, S. & Abraham, J. A., Mar 30 2009, Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems. p. 77-82 6 p. 4749656. (Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
Computer hardware description languages
System-on-chip

STAR: Generating input vectors for design validation by Static analysis of RTL

Lui, L. & Vasudevan, S., Nov 18 2009, HLDVT'09 - IEEE International High Level Design Validation and Test Workshop, Conference Proceedings. p. 32-37 6 p. 5340179. (Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Static analysis
Static Analysis
Concretes
Simulation
Coverage
2007

Efficient microprocessor verification using antecedent conditioned slicing

Vasudevan, S., Viswanath, V. & Abraham, J. A., Dec 1 2007, Proceedings - 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems. p. 43-49 7 p. 4092021. (Proceedings of the IEEE International Conference on VLSI Design).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Microprocessor chips
Computer hardware description languages
Model checking
Engines
Specifications
2006

Automatic decomposition for sequential equivalence checking of system level and RTL descriptions

Vasudevan, S., Viswanath, V., Abraham, J. A. & Tu, J., Dec 1 2006, Proceedings - Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, MEMOCODE'06. p. 71-80 10 p. 1695903. (Proceedings - Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, MEMOCODE'06).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Decomposition
Computer hardware description languages

Automatic generation of instruction sequences targeting hard-to-detect structural faults in a processor

Gurumurthy, S., Vasudevan, S. & Abraham, J. A., Jan 1 2006, 2006 IEEE International Test Conference, ITC. Institute of Electrical and Electronics Engineers Inc., 4079354. (Proceedings - International Test Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Model checking
Engines
Testing
2005

Automated mapping of pre-computed module-level test sequences to processor instructions

Gurumurthy, S., Vasudevan, S. & Abraham, J. A., Dec 1 2005, IEEE International Test Conference, Proceedings, ITC 2005. p. 294-303 10 p. 1583987. (Proceedings - International Test Conference; vol. 2005).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Temporal logic
Module
Fault
Defects
Temporal Logic
2004

Static program transformations for efficient software model checking

Vasudevan, S. & Abraham, J. A., Jan 1 2004, Building the Information Society - IFIP 18th World Computer Congress Topical Sessions. Springer New York LLC, p. 257-281 25 p. (IFIP Advances in Information and Communication Technology; vol. 156).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Model checking
Temporal logic
Formal methods
Syntactics
Explosions