Rakesh Kumar

20022019

Research output per year

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Research Output

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2019
2018

Bespoke Processors for Applications with Ultra-Low Area and Power Constraints

Cherupalli, H., Duwe, H., Ye, W., Kumar, R. & Sartori, J., May 1 2018, In : IEEE Micro. 38, 3, p. 32-39 8 p.

Research output: Contribution to journalArticle

Temporal integration of emulation and network simulators on linux multiprocessors

Lamps, J., Babu, V., Nicol, D. M., Adam, V. & Kumar, R., Jan 2018, In : ACM Transactions on Modeling and Computer Simulation. 28, 1, 1.

Research output: Contribution to journalArticle

2017

Determining application-specific peak power and energy requirements for ultra-low-power processors

Cherupalli, H., Duwe, H., Ye, W., Kumar, R. & Sartori, J., Dec 2017, In : ACM Transactions on Computer Systems. 35, 3, 9.

Research output: Contribution to journalArticle

2014

Better-than-worst-case design: Progress and opportunities

Cong, J., Duwe, H., Kumar, R. & Li, S., Jan 2014, In : Journal of Computer Science and Technology. 29, 4, p. 656-663 8 p.

Research output: Contribution to journalArticle

Markov chain algorithms: A template for building future robust low-power systems

Deka, B., Birklykke, A. A., Duwe, H., Mansinghka, V. K. & Kumar, R., Jun 28 2014, In : Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences. 372, 2018

Research output: Contribution to journalArticle

Triply resonant four-wave mixing in silicon-coupled resonator microring waveguides

Ong, J. R., Kumar, R. & Mookherjea, S., Oct 1 2014, In : Optics Letters. 39, 19, p. 5653-5656 4 p.

Research output: Contribution to journalArticle

2013

Branch and data herding: Reducing control and memory divergence for error-tolerant GPU applications

Sartori, J. & Kumar, R., Jan 28 2013, In : IEEE Transactions on Multimedia. 15, 2, p. 279-290 12 p., 6376229.

Research output: Contribution to journalArticle

Enhancing the efficiency of energy-constrained DVFS designs

Kahng, A. B., Kang, S., Kumar, R. & Sartori, J., Jan 1 2013, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 21, 10, p. 1769-1782 14 p., 6352933.

Research output: Contribution to journalArticle

Exploiting timing error resilience in processor architecture

Sartori, J. & Kumar, R., May 1 2013, In : Transactions on Embedded Computing Systems. 12, 2 SUPPL., 89.

Research output: Contribution to journalArticle

High performance, energy efficient chipkill correct memory with multidimensional parity

Jian, X., Sartori, J., Duwe, H. & Kumar, R., Jul 1 2013, In : IEEE Computer Architecture Letters. 12, 2, p. 39-42 4 p., 6231590.

Research output: Contribution to journalArticle

Underdesigned and opportunistic computing in presence of hardware variability

Gupta, P., Agarwal, Y., Dolecek, L., Dutt, N., Gupta, R. K., Kumar, R., Mitra, S., Nicolau, A., Rosing, T. S., Srivastava, M. B., Swanson, S. & Sylvester, D., Jan 7 2013, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 32, 1, p. 8-23 16 p., 6387697.

Research output: Contribution to journalArticle

2012

Recovery-driven design: Exploiting error resilience in design of energy-efficient processors

Kahng, A. B., Kang, S., Kumar, R. & Sartori, J., Mar 1 2012, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 31, 3, p. 404-417 14 p., 6152777.

Research output: Contribution to journalArticle

2011

MOPED: Accelerating data communication on future CMPs

Gu, J., Sun, Y., Lumetta, S. S. & Kumar, R., Jul 1 2011, In : IEEE Micro. 31, 4, p. 42-50 9 p., 5887310.

Research output: Contribution to journalArticle

Stochastic computing

Sartori, J. & Kumar, R., Dec 1 2011, In : Foundations and Trends in Electronic Design Automation. 5, 3, p. 153-210 58 p.

Research output: Contribution to journalArticle

2010

A workload-adaptive and reconfigurable bus architecture for multicore processors

Chen, D., Akram, S., Papakonstantinou, A. & Kumar, R., Nov 22 2010, In : International Journal of Reconfigurable Computing. 2010, 205852.

Research output: Contribution to journalArticle

2005

Heterogeneous chip multiprocessors

Kumar, R., Tullsen, D. M., Jouppi, N. P. & Ranganathan, P., Nov 1 2005, Computer, 38, 11, p. 32-38 7 p.

Research output: Contribution to specialist publicationArticle

The Danger of Interval-Based Power Efficiency Metrics: When Worst Is Best

Sazeides, Y., Constantinou, T., Kumar, R. & Tullsen, D. M., Jan 2005, In : IEEE Computer Architecture Letters. 4, 1, p. 1-4 4 p.

Research output: Contribution to journalArticle

2003

Processor power reduction via single-isa heterogeneous multi-core architectures

Kumar, R., Tullsen, D. M., Jouppi, N. P. & Ranganathan, P., Jan 1 2003, In : IEEE Computer Architecture Letters. 2, 1, 1 p.

Research output: Contribution to journalArticle