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2020

A 12-Gb/s 10-ns Turn-On Time Rapid ON/OFF Baud-Rate DFE Receiver in 65-nm CMOS

Kim, D., Ahmed, M. G., Choi, W. S., Elkholy, A. & Hanumolu, P. K., Jan 1 2020, (Accepted/In press) In : IEEE Journal of Solid-State Circuits.

Research output: Contribution to journalArticle

A Low-Noise Frequency Synthesizer Using Multiphase Generation and Combining Techniques

Khashaba, A., Elkholy, A., Megawer, K. M., Ahmed, M. G. & Hanumolu, P. K., Mar 2020, In : IEEE Journal of Solid-State Circuits. 55, 3, p. 592-601 10 p., 8903272.

Research output: Contribution to journalArticle

2019

34-GBD linear transimpedance amplifier for 200-Gb/s DP-16-QAM optical coherent receivers

Ahmed, M. G., Huynh, T. N., Williams, C., Wang, Y., Hanumolu, P. K. & Rylyakov, A., Mar 2019, In : IEEE Journal of Solid-State Circuits. 54, 3, p. 834-844 11 p., 8570782.

Research output: Contribution to journalArticle

A 0.016 mm2 0.26-μ W/MHz 60-240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS

Zhu, J., Choi, W. S. & Hanumolu, P. K., Aug 2019, In : IEEE Journal of Solid-State Circuits. 54, 8, p. 2186-2194 9 p., 8723106.

Research output: Contribution to journalArticle

A 15-Gb/s sub-baud-rate digital CDR

Kim, D., Choi, W. S., Elkholy, A., Kenney, J. & Hanumolu, P. K., Mar 2019, In : IEEE Journal of Solid-State Circuits. 54, 3, p. 685-695 11 p., 8599124.

Research output: Contribution to journalArticle

A 2.5-5.75-GHz Ring-Based Injection-Locked Clock Multiplier with Background-Calibrated Reference Frequency Doubler

Elkholy, A., Coombs, D., Nandwana, R. K., Elmallah, A. & Hanumolu, P. K., Jul 2019, In : IEEE Journal of Solid-State Circuits. 54, 7, p. 2049-2058 10 p., 8691469.

Research output: Contribution to journalArticle

A 6 μ W ±50 ppm/°C ±1500 ppm/V 1.5 MHz RC oscillator using self-regulation

Wang, T., Griffith, D., Ahmed, M. G., Zhu, J., Wei, D., Elkholy, A., Elmallah, A. & Hanumolu, P. K., Aug 2019, In : IEEE Transactions on Circuits and Systems II: Express Briefs. 66, 8, p. 1297-1301 5 p., 8556499.

Research output: Contribution to journalArticle

A Fast Startup CMOS Crystal Oscillator Using Two-Step Injection

Megawer, K. M., Pal, N., Elkholy, A., Ahmed, M. G., Khashaba, A., Griffith, D. & Hanumolu, P. K., Dec 2019, In : IEEE Journal of Solid-State Circuits. 54, 12, p. 3257-3268 12 p., 8827914.

Research output: Contribution to journalArticle

Design of crystal-oscillator frequency quadrupler for low-jitter clock multipliers

Megawer, K. M., Elkholy, A., Gamal Ahmed, M., Elmallah, A. & Kumar Hanumolu, P., Jan 2019, In : IEEE Journal of Solid-State Circuits. 54, 1, p. 65-74 10 p., 8486730.

Research output: Contribution to journalArticle

2018

A 0.45-0.7 v 1-6 Gb/s 0.29-0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation

Choi, W. S., Shu, G., Talegaonkar, M., Liu, Y., Wei, D., Benini, L. & Hanumolu, P. K., Mar 2018, In : IEEE Journal of Solid-State Circuits. 53, 3, p. 884-895 12 p.

Research output: Contribution to journalArticle

A 10-Gb/s/ch, 0.6-pJ/bit/mm Power Scalable Rapid-ON/OFF Transceiver for On-Chip Energy Proportional Interconnects

Wei, D., Anand, T., Shu, G., Schutt-Ainé, J. E. & Hanumolu, P. K., Mar 2018, In : IEEE Journal of Solid-State Circuits. 53, 3, p. 873-883 11 p.

Research output: Contribution to journalArticle

A 10-MHz 2-800-mA 0.5-1.5-V 90% Peak Efficiency Time-Based Buck Converter with Seamless Transition between PWM/PFM Modes

Kim, S. J., Choi, W. S., Pilawa-Podgurski, R. & Hanumolu, P. K., Mar 2018, In : IEEE Journal of Solid-State Circuits. 53, 3, p. 814-824 11 p.

Research output: Contribution to journalArticle

A 12-Gb/s -16.8-dBm OMA Sensitivity 23-mW Optical Receiver in 65-nm CMOS

Ahmed, M. G., Talegaonkar, M., Elkholy, A., Shu, G., Elmallah, A., Rylyakov, A. & Hanumolu, P. K., Feb 2018, In : IEEE Journal of Solid-State Circuits. 53, 2, p. 445-457 13 p., 8074728.

Research output: Contribution to journalArticle

A 6.75-8.25-GHz -250-dB FoM Rapid ON/OFF Fractional-N Injection-Locked Clock Multiplier

Elkholy, A., Elmallah, A., Ahmed, M. G. & Hanumolu, P. K., Jun 2018, In : IEEE Journal of Solid-State Circuits. 53, 6, p. 1818-1829 12 p.

Research output: Contribution to journalArticle

A modulo-based architecture for analog-to-digital conversion

Ordentlich, O., Tabak, G., Hanumolu, P. K., Singer, A. C. & Wornell, G. W., Oct 2018, In : IEEE Journal on Selected Topics in Signal Processing. 12, 5, p. 825-840 16 p., 8425696.

Research output: Contribution to journalArticle

Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers

Elkholy, A., Saxena, S., Shu, G., Elshazly, A. & Hanumolu, P. K., Jun 2018, In : IEEE Journal of Solid-State Circuits. 53, 6, p. 1806-1817 12 p.

Research output: Contribution to journalArticle

2017

A 0.0021 mm2 1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS

Zhu, J., Nandwana, R. K., Shu, G., Elkholy, A., Kim, S. J. & Hanumolu, P. K., Jan 2017, In : IEEE Journal of Solid-State Circuits. 52, 1, p. 8-20 13 p., 7564468.

Research output: Contribution to journalArticle

A 1-to-2048 fully-integrated cascaded digital frequency synthesizer for low frequency reference clocks using scrambling TDC

Nandwana, R. K., Saxena, S., Elshazly, A., Mayaram, K. & Hanumolu, P. K., Feb 2017, In : IEEE Transactions on Circuits and Systems I: Regular Papers. 64, 2, p. 283-295 13 p., 7731190.

Research output: Contribution to journalArticle

A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver

Saxena, S., Shu, G., Nandwana, R. K., Talegaonkar, M., Elkholy, A., Anand, T., Choi, W. S. & Hanumolu, P. K., May 2017, In : IEEE Journal of Solid-State Circuits. 52, 5, p. 1399-1411 13 p., 7890481.

Research output: Contribution to journalArticle

A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS

Talegaonkar, M., Anand, T., Elkholy, A., Elshazly, A., Nandwana, R. K., Saxena, S., Young, B., Choi, W. S. & Hanumolu, P. K., Sep 2017, In : IEEE Journal of Solid-State Circuits. 52, 9, p. 2306-2320 15 p., 7999180.

Research output: Contribution to journalArticle

2016

A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL with Extended Range Multi-Modulus Divider

Elkholy, A., Saxena, S., Nandwana, R. K., Elshazly, A. & Hanumolu, P. K., Aug 2016, In : IEEE Journal of Solid-State Circuits. 51, 8, p. 1771-1784 14 p., 7489022.

Research output: Contribution to journalArticle

A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition

Shu, G., Choi, W. S., Saxena, S., Talegaonkar, M., Anand, T., Elkholy, A., Elshazly, A. & Hanumolu, P. K., Feb 1 2016, In : IEEE Journal of Solid-State Circuits. 51, 2, p. 428-439 12 p., 7362125.

Research output: Contribution to journalArticle

A VCO Based Highly Digital Temperature Sensor with 0.034 °c/mV Supply Sensitivity

Anand, T., Makinwa, K. A. A. & Hanumolu, P. K., Nov 2016, In : IEEE Journal of Solid-State Circuits. 51, 11, p. 2651-2663 13 p.

Research output: Contribution to journalArticle

2015

A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC

Elkholy, A., Anand, T., Choi, W. S., Elshazly, A. & Hanumolu, P. K., Apr 1 2015, In : IEEE Journal of Solid-State Circuits. 50, 4, p. 867-881 15 p., 7027236.

Research output: Contribution to journalArticle

A 4-Phase 30-70 MHz Switching Frequency Buck Converter Using a Time-Based Compensator

Kim, S. J., Nandwana, R. K., Khan, Q., Pilawa Podgurski, R. C. N. & Hanumolu, P. K., Dec 2015, In : IEEE Journal of Solid-State Circuits. 50, 12, p. 2814-2824 11 p., 7182789.

Research output: Contribution to journalArticle

A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links

Anand, T., Talegaonkar, M., Elkholy, A., Saxena, S., Elshazly, A. & Hanumolu, P. K., Dec 2015, In : IEEE Journal of Solid-State Circuits. 50, 12, p. 3101-3119 19 p., 7265108.

Research output: Contribution to journalArticle

A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links

Choi, W. S., Anand, T., Shu, G., Elshazly, A. & Hanumolu, P. K., Mar 1 2015, In : IEEE Journal of Solid-State Circuits. 50, 3, p. 737-748 12 p., 7042350.

Research output: Contribution to journalArticle

A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method

Nandwana, R. K., Anand, T., Saxena, S., Kim, S. J., Talegaonkar, M., Elkholy, A., Choi, W. S., Elshazly, A. & Hanumolu, P. K., Apr 1 2015, In : IEEE Journal of Solid-State Circuits. 50, 4, p. 882-895 14 p., 7029717.

Research output: Contribution to journalArticle

A highly digital VCO-Based ADC architecture for current sensing applications

Prabha, P., Kim, S. J., Reddy, K., Rao, S., Griesert, N., Rao, A., Winter, G. & Hanumolu, P. K., Aug 1 2015, In : IEEE Journal of Solid-State Circuits. 50, 8, p. 1785-1795 11 p., 7084688.

Research output: Contribution to journalArticle

Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers

Elkholy, A., Talegaonkar, M., Anand, T. & Hanumolu, P. K., Dec 2015, In : IEEE Journal of Solid-State Circuits. 50, 12, p. 3160-3174 15 p., 7297803.

Research output: Contribution to journalArticle

High Frequency Buck Converter Design Using Time-Based Control Techniques

Kim, S. J., Khan, Q., Talegaonkar, M., Elshazly, A., Rao, A., Griesert, N., Winter, G., McIntyre, W. & Hanumolu, P. K., Apr 1 2015, In : IEEE Journal of Solid-State Circuits. 50, 4, p. 990-1001 12 p., 6998097.

Research output: Contribution to journalArticle

2014

A 5 Gb/s, 10 ns power-on-time, 36 μw off-state power, fast power-on transmitter for energy proportional links

Anand, T., Elshazly, A., Talegaonkar, M., Young, B. & Hanumolu, P. K., Oct 1 2014, In : IEEE Journal of Solid-State Circuits. 49, 10, p. 2243-2258 16 p., 6887370.

Research output: Contribution to journalArticle

A 5 Gb/s energy-efficient voltage-mode transmitter using time-based de-emphasis

Saxena, S., Nandwana, R. K. & Hanumolu, P. K., Aug 2014, In : IEEE Journal of Solid-State Circuits. 49, 8, p. 1827-1836 10 p., 6809856.

Research output: Contribution to journalArticle

A deterministic digital background calibration technique for VCO-based ADCs

Rao, S., Reddy, K., Young, B. & Hanumolu, P. K., Apr 2014, In : IEEE Journal of Solid-State Circuits. 49, 4, p. 950-960 11 p., 6712154.

Research output: Contribution to journalArticle

An 8 Gb/s-64 Mb/s, 2.3-4.2 mW/Gb/s Burst-Mode Transmitter in 90 nm CMOS

Talegaonkar, M., Elshazly, A., Reddy, K., Prabha, P., Anand, T. & Hanumolu, P. K., Oct 1 2014, In : IEEE Journal of Solid-State Circuits. 49, 10, p. 2228-2242 15 p., 6893043.

Research output: Contribution to journalArticle

A noise-shaping time-to-digital converter using switched-ring oscillators - Analysis, design, and measurement techniques

Elshazly, A., Rao, S., Young, B. & Hanumolu, P. K., May 2014, In : IEEE Journal of Solid-State Circuits. 49, 5, p. 1184-1197 14 p., 6748928.

Research output: Contribution to journalArticle

A reference-less clock and data recovery circuit using phase-rotating phase-locked loop

Shu, G., Saxena, S., Choi, W. S., Talegaonkar, M., Inti, R., Elshazly, A., Young, B. & Hanumolu, P. K., Apr 2014, In : IEEE Journal of Solid-State Circuits. 49, 4, p. 1036-1047 12 p., 6712167.

Research output: Contribution to journalArticle

2013

An 80-dB DR, 7.2-MHz bandwidth single opamp biquad based CT Δ Σ modulator dissipating 13.7-mW

Zanbaghi, R., Hanumolu, P. K. & Fiez, T. S., Jan 1 2013, In : IEEE Journal of Solid-State Circuits. 48, 2, p. 487-501 15 p., 6375770.

Research output: Contribution to journalArticle

Clock multiplication techniques using digital multiplying delay-locked loops

Elshazly, A., Inti, R., Young, B. & Hanumolu, P. K., May 15 2013, In : IEEE Journal of Solid-State Circuits. 48, 6, p. 1416-1428 13 p., 6515347.

Research output: Contribution to journalArticle

2012

A 12.5-bit 4 MHz 13.8 mW MASH Δ Σ modulator with multirated VCO-based ADC

Zaliasl, S., Saxena, S., Hanumolu, P. K., Mayaram, K. & Fiez, T. S., Jul 25 2012, In : IEEE Transactions on Circuits and Systems I: Regular Papers. 59, 8, p. 1604-1613 10 p., 6243235.

Research output: Contribution to journalArticle

A 16-mW 78-dB SNDR 10-MHz BW CT Δσ ADC Using Residue-Cancelling VCO-Based Quantizer

Reddy, K., Rao, S., Inti, R., Young, B., Elshazly, A., Talegaonkar, M. & Hanumolu, P. K., Nov 12 2012, In : IEEE Journal of Solid-State Circuits. 47, 12, p. 2916-2927 12 p., 6338303.

Research output: Contribution to journalArticle

A multiplexer-based digital passive linear counter (PLINCO)

Weaver, S., Hershberg, B., Hanumolu, P. K. & Moon, U. K., Oct 1 2012, In : Analog Integrated Circuits and Signal Processing. 73, 1, p. 143-149 7 p.

Research output: Contribution to journalArticle

Analog filter design using ring oscillator integrators

Drost, B., Talegaonkar, M. & Hanumolu, P. K., Dec 5 2012, In : IEEE Journal of Solid-State Circuits. 47, 12, p. 3120-3129 10 p., 6365770.

Research output: Contribution to journalArticle

A semi-synchronous SAR ADC

Tong, T., Hanumolu, P. K. & Temes, G. C., Jan 1 2012, In : Analog Integrated Circuits and Signal Processing. 71, 3, p. 407-410 4 p.

Research output: Contribution to journalArticle

Calibration technique for SAR analog-to-digital converters

Tong, T., Yu, W., Hanumolu, P. K. & Temes, G. C., Oct 1 2012, In : Analog Integrated Circuits and Signal Processing. 73, 1, p. 301-309 9 p.

Research output: Contribution to journalArticle

Rail-to-rail input pipelined ADC incorporating multistage signal mapping

Sasidhar, N., Gubbins, D., Hanumolu, P. K. & Moon, U. K., Sep 5 2012, In : IEEE Transactions on Circuits and Systems II: Express Briefs. 59, 9, p. 558-562 5 p., 6287564.

Research output: Contribution to journalArticle

2011

A 0.4-to-3 GHz digital PLL with PVT insensitive supply noise cancellation using deterministic background calibration

Elshazly, A., Inti, R., Yin, W., Young, B. & Hanumolu, P. K., Dec 1 2011, In : IEEE Journal of Solid-State Circuits. 46, 12, p. 2759-2771 13 p., 5993463.

Research output: Contribution to journalArticle

A 0.5-to-2.5 Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance

Inti, R., Yin, W., Elshazly, A., Sasidhar, N. & Hanumolu, P. K., Dec 1 2011, In : IEEE Journal of Solid-State Circuits. 46, 12, p. 3150-3162 13 p., 6069580.

Research output: Contribution to journalArticle

A 0.7-to-3.5 GHz 0.6-to-2.8 mW highly digital phase-locked loop with bandwidth tracking

Yin, W., Inti, R., Elshazly, A., Young, B. & Hanumolu, P. K., Aug 1 2011, In : IEEE Journal of Solid-State Circuits. 46, 8, p. 1870-1880 11 p., 5892905.

Research output: Contribution to journalArticle