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Research Output

2015

A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS

Reddy, K., Dey, S., Rao, S., Young, B., Prabha, P. & Hanumolu, P. K., Aug 31 2015, 2015 Symposium on VLSI Circuits, VLSI Circuits 2015. Institute of Electrical and Electronics Engineers Inc., p. C256-C257 7231278. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; vol. 2015-August).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A 6.75-to-8.25GHz 2.25mW 190fsrms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS

Elkholy, A., Talegaonkar, M., Anand, T. & Hanumolu, P. K., Mar 17 2015, 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., p. 188-189 2 p. 7062989. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 58).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links

Anand, T., Talegaonkar, M., Elkholy, A., Saxena, S., Elshazly, A. & Hanumolu, P. K., Dec 2015, In : IEEE Journal of Solid-State Circuits. 50, 12, p. 3101-3119 19 p., 7265108.

Research output: Contribution to journalArticle

A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS

Anand, T., Talegaonkar, M., Elkholy, A., Saxena, S., Elshazly, A. & Hanumolu, P. K., Mar 17 2015, 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., p. 64-65 2 p. 7062927. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 58).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links

Choi, W. S., Anand, T., Shu, G., Elshazly, A. & Hanumolu, P. K., Mar 1 2015, In : IEEE Journal of Solid-State Circuits. 50, 3, p. 737-748 12 p., 7042350.

Research output: Contribution to journalArticle

A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method

Nandwana, R. K., Anand, T., Saxena, S., Kim, S. J., Talegaonkar, M., Elkholy, A., Choi, W. S., Elshazly, A. & Hanumolu, P. K., Apr 1 2015, In : IEEE Journal of Solid-State Circuits. 50, 4, p. 882-895 14 p., 7029717.

Research output: Contribution to journalArticle

A highly digital VCO-Based ADC architecture for current sensing applications

Prabha, P., Kim, S. J., Reddy, K., Rao, S., Griesert, N., Rao, A., Winter, G. & Hanumolu, P. K., Aug 1 2015, In : IEEE Journal of Solid-State Circuits. 50, 8, p. 1785-1795 11 p., 7084688.

Research output: Contribution to journalArticle

A self-referenced VCO-based temperature sensor with 0.034°C/mV supply sensitivity in 65nm CMOS

Anand, T., Makinwa, K. A. A. & Hanumolu, P. K., Aug 31 2015, 2015 Symposium on VLSI Circuits, VLSI Circuits 2015. Institute of Electrical and Electronics Engineers Inc., p. C200-C201 7231257. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; vol. 2015-August).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers

Elkholy, A., Talegaonkar, M., Anand, T. & Hanumolu, P. K., Dec 2015, In : IEEE Journal of Solid-State Circuits. 50, 12, p. 3160-3174 15 p., 7297803.

Research output: Contribution to journalArticle

High Frequency Buck Converter Design Using Time-Based Control Techniques

Kim, S. J., Khan, Q., Talegaonkar, M., Elshazly, A., Rao, A., Griesert, N., Winter, G., McIntyre, W. & Hanumolu, P. K., Apr 1 2015, In : IEEE Journal of Solid-State Circuits. 50, 4, p. 990-1001 12 p., 6998097.

Research output: Contribution to journalArticle

Low dropout regulators

Hanumolu, P. K., Nov 25 2015, 2015 IEEE Custom Integrated Circuits Conference, CICC 2015. Institute of Electrical and Electronics Engineers Inc., 7338435. (Proceedings of the Custom Integrated Circuits Conference; vol. 2015-November).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2014

15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS

Elkholy, A., Elshazly, A., Saxena, S., Shu, G. & Hanumolu, P. K., Apr 14 2014, 2014 IEEE International Solid-State Circuits Conference, ISSCC 2014 - Digest of Technical Papers. p. 272-273 2 p. 6757431. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 57).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS

Shu, G., Choi, W. S., Saxena, S., Anand, T., Elshazly, A. & Hanumolu, P. K., Apr 14 2014, 2014 IEEE International Solid-State Circuits Conference, ISSCC 2014 - Digest of Technical Papers. p. 150-151 2 p. 6757377. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 57).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A 10-25MHz, 600mA buck converter using time-based PID compensator with 2μA/MHz quiescent current, 94% peak efficiency, and 1MHz BW

Khan, Q., Kim, S. J., Talegaonkar, M., Elshazly, A., Rao, A., Griesert, N., Winter, G., McIntyre, W. & Hanumolu, P. K., Jan 1 2014, 2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 6858439. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with-106dBc/Hz In-band noise using time amplifier based TDC

Elkholy, A., Anand, T., Choi, W. S., Elshazly, A. & Hanumolu, P. K., Jan 1 2014, 2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 6858391. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement

Nandwana, R. K., Anand, T., Saxena, S., Kim, S. J., Talegaonkar, M., Elkholy, A., Choi, W. S., Elshazly, A. & Hanumolu, P. K., Jan 1 2014, 2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 6858446. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter

Talegaonkar, M., Anand, T., Elkholy, A., Elshazly, A., Nandwana, R. K., Saxena, S., Young, B., Choi, W. & Hanumolu, P. K., Jan 1 2014, 2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 6858392. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A 5 Gb/s, 10 ns power-on-time, 36 μw off-state power, fast power-on transmitter for energy proportional links

Anand, T., Elshazly, A., Talegaonkar, M., Young, B. & Hanumolu, P. K., Oct 1 2014, In : IEEE Journal of Solid-State Circuits. 49, 10, p. 2243-2258 16 p., 6887370.

Research output: Contribution to journalArticle

A 5 Gb/s energy-efficient voltage-mode transmitter using time-based de-emphasis

Saxena, S., Nandwana, R. K. & Hanumolu, P. K., Aug 2014, In : IEEE Journal of Solid-State Circuits. 49, 8, p. 1827-1836 10 p., 6809856.

Research output: Contribution to journalArticle

A 75dB DR 50MHz BW 3rd order CT-ΔΣ modulator using VCO-based integrators

Young, B., Reddy, K., Rao, S., Elshazly, A., Anand, T. & Hanumolu, P. K., Jan 1 2014, 2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 6858395. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A deterministic digital background calibration technique for VCO-based ADCs

Rao, S., Reddy, K., Young, B. & Hanumolu, P. K., Apr 2014, In : IEEE Journal of Solid-State Circuits. 49, 4, p. 950-960 11 p., 6712154.

Research output: Contribution to journalArticle

An 8 Gb/s-64 Mb/s, 2.3-4.2 mW/Gb/s Burst-Mode Transmitter in 90 nm CMOS

Talegaonkar, M., Elshazly, A., Reddy, K., Prabha, P., Anand, T. & Hanumolu, P. K., Oct 1 2014, In : IEEE Journal of Solid-State Circuits. 49, 10, p. 2228-2242 15 p., 6893043.

Research output: Contribution to journalArticle

A noise-shaping time-to-digital converter using switched-ring oscillators - Analysis, design, and measurement techniques

Elshazly, A., Rao, S., Young, B. & Hanumolu, P. K., May 2014, In : IEEE Journal of Solid-State Circuits. 49, 5, p. 1184-1197 14 p., 6748928.

Research output: Contribution to journalArticle

A reference-less clock and data recovery circuit using phase-rotating phase-locked loop

Shu, G., Saxena, S., Choi, W. S., Talegaonkar, M., Inti, R., Elshazly, A., Young, B. & Hanumolu, P. K., Apr 2014, In : IEEE Journal of Solid-State Circuits. 49, 4, p. 1036-1047 12 p., 6712167.

Research output: Contribution to journalArticle

A VCO-based current-to-digital converter for sensor applications

Prabha, P., Kim, S. J., Reddy, K., Rao, S., Griesert, N., Rao, A., Winter, G. & Hanumolu, P. K., Nov 4 2014, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014. Institute of Electrical and Electronics Engineers Inc., 6945990. (Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Introduction to the special issue on the 2014 IEEE international solid-state circuits conferences (ISSCC)

Nagata, M., Breems, L. J., Samori, C., Mattisson, S. & Hanumolu, P. K., Dec 1 2014, In : IEEE Journal of Solid-State Circuits. 49, 12, p. 2743-2747 5 p., 6951480.

Research output: Contribution to journalEditorial

2013

A 2.5GHz 2.2mW/25μW on/off-state power 2psrms-long-term- jitter digital clock multiplier with 3-reference-cycles power-on time

Anand, T., Talegaonkar, M., Elshazly, A., Young, B. & Hanumolu, P. K., Apr 29 2013, 2013 IEEE International Solid-State Circuits Conference, ISSCC 2013 - Digest of Technical Papers. p. 256-257 2 p. 6487724. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 56).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A 2.5GHz 5.4mW 1-to-2048 digital clock multiplier using a scrambling TDC

Nandwana, R. K., Saxena, S., Elshazly, A., Mayaram, K. & Hanumolu, P. K., Sep 17 2013, 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers. p. C156-C157 6578645. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A 4.1mW, 12-bit ENOB, 5MHz BW, VCO-based ADC with on-chip deterministic digital background calibration in 90nm CMOS

Rao, S., Reddy, K., Young, B. & Hanumolu, P. K., Sep 17 2013, 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers. 6578723. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A 5Gb/s 2.6mW/Gb/s reference-less half-rate PRPLL-based digital CDR

Shu, G., Saxena, S., Choi, W. S., Talegaonkar, M., Inti, R., Elshazly, A., Young, B. & Hanumolu, P. K., Sep 17 2013, 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers. p. C278-C279 6578694. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A 5 Gb/s 3.2 mW/Gb/s 28 dB loss-compensating pulse-width modulated voltage-mode transmitter

Saxena, S., Nandwana, R. K. & Hanumolu, P. K., Nov 7 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013. Institute of Electrical and Electronics Engineers Inc., 6658403. (Proceedings of the Custom Integrated Circuits Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A fast power-on 2.2Gb/s burst-mode digital CDR with programmable input jitter filtering

Choi, W. S., Anand, T., Shu, G. & Hanumolu, P. K., Sep 17 2013, 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers. p. C280-C281 6578695. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

An 80-dB DR, 7.2-MHz bandwidth single opamp biquad based CT Δ Σ modulator dissipating 13.7-mW

Zanbaghi, R., Hanumolu, P. K. & Fiez, T. S., Jan 1 2013, In : IEEE Journal of Solid-State Circuits. 48, 2, p. 487-501 15 p., 6375770.

Research output: Contribution to journalArticle

Clock multiplication techniques using digital multiplying delay-locked loops

Elshazly, A., Inti, R., Young, B. & Hanumolu, P. K., May 15 2013, In : IEEE Journal of Solid-State Circuits. 48, 6, p. 1416-1428 13 p., 6515347.

Research output: Contribution to journalArticle

2012

A 0.55V 61dB-SNR 67dB-SFDR 7MHz 4 th-order Butterworth filter using ring-oscillator-based integrators in 90nm CMOS

Drost, B., Talegaonkar, M. & Hanumolu, P. K., 2012, 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers. Vol. 55. p. 360-361 2 p. 6177051

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A 1.5GHz 1.35mW -112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity

Elshazly, A., Inti, R., Talegaonkar, M. & Hanumolu, P. K., Sep 28 2012, 2012 Symposium on VLSI Circuits, VLSIC 2012. p. 188-189 2 p. 6243853. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A 1.5GHz 890μW digital MDLL with 400fs rms integrated jitter, -55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDC

Elshazly, A., Inti, R., Young, B. & Hanumolu, P. K., May 11 2012, 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers. p. 242-243 2 p. 6176993. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 55).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A 12.5-bit 4 MHz 13.8 mW MASH Δ Σ modulator with multirated VCO-based ADC

Zaliasl, S., Saxena, S., Hanumolu, P. K., Mayaram, K. & Fiez, T. S., Jul 25 2012, In : IEEE Transactions on Circuits and Systems I: Regular Papers. 59, 8, p. 1604-1613 10 p., 6243235.

Research output: Contribution to journalArticle

A 13b 315fs rms 2mW 500MS/s 1MHz bandwidth highly digital time-to-digital converter using switched ring oscillators

Elshazly, A., Rao, S., Young, B. & Hanumolu, P. K., 2012, 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers. Vol. 55. p. 464-465 2 p. 6177092

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer

Reddy, K., Rao, S., Inti, R., Young, B., Elshazly, A., Talegaonkar, M. & Hanumolu, P. K., May 11 2012, 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers. p. 152-153 2 p. 6176955. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 55).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A 16-mW 78-dB SNDR 10-MHz BW CT Δσ ADC Using Residue-Cancelling VCO-Based Quantizer

Reddy, K., Rao, S., Inti, R., Young, B., Elshazly, A., Talegaonkar, M. & Hanumolu, P. K., Nov 12 2012, In : IEEE Journal of Solid-State Circuits. 47, 12, p. 2916-2927 12 p., 6338303.

Research output: Contribution to journalArticle

A 900mA 93% efficient 50μA quiescent current fixed frequency hysteretic buck converter using a highly digital hybrid voltage- and current-mode control

Khan, Q., Elshazly, A., Rao, S., Inti, R. & Hanumolu, P. K., Sep 28 2012, 2012 Symposium on VLSI Circuits, VLSIC 2012. p. 182-183 2 p. 6243850. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A multiplexer-based digital passive linear counter (PLINCO)

Weaver, S., Hershberg, B., Hanumolu, P. K. & Moon, U. K., Oct 1 2012, In : Analog Integrated Circuits and Signal Processing. 73, 1, p. 143-149 7 p.

Research output: Contribution to journalArticle

Analog filter design using ring oscillator integrators

Drost, B., Talegaonkar, M. & Hanumolu, P. K., Dec 5 2012, In : IEEE Journal of Solid-State Circuits. 47, 12, p. 3120-3129 10 p., 6365770.

Research output: Contribution to journalArticle

A semi-synchronous SAR ADC

Tong, T., Hanumolu, P. K. & Temes, G. C., Jan 1 2012, In : Analog Integrated Circuits and Signal Processing. 71, 3, p. 407-410 4 p.

Research output: Contribution to journalArticle

Calibration technique for SAR analog-to-digital converters

Tong, T., Yu, W., Hanumolu, P. K. & Temes, G. C., Sep 28 2012, p. 2993-2996. 4 p.

Research output: Contribution to conferencePaper

Calibration technique for SAR analog-to-digital converters

Tong, T., Yu, W., Hanumolu, P. K. & Temes, G. C., Oct 1 2012, In : Analog Integrated Circuits and Signal Processing. 73, 1, p. 301-309 9 p.

Research output: Contribution to journalArticle

Rail-to-rail input pipelined ADC incorporating multistage signal mapping

Sasidhar, N., Gubbins, D., Hanumolu, P. K. & Moon, U. K., Sep 5 2012, In : IEEE Transactions on Circuits and Systems II: Express Briefs. 59, 9, p. 558-562 5 p., 6287564.

Research output: Contribution to journalArticle

2011

A 0.4-to-3 GHz digital PLL with PVT insensitive supply noise cancellation using deterministic background calibration

Elshazly, A., Inti, R., Yin, W., Young, B. & Hanumolu, P. K., Dec 1 2011, In : IEEE Journal of Solid-State Circuits. 46, 12, p. 2759-2771 13 p., 5993463.

Research output: Contribution to journalArticle

A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration

Elshazly, A., Inti, R., Yin, W., Young, B. & Hanumolu, P. K., May 12 2011, 2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011. p. 92-93 2 p. 5746233. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution