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Research Output

2020

A 12-Gb/s 10-ns Turn-On Time Rapid ON/OFF Baud-Rate DFE Receiver in 65-nm CMOS

Kim, D., Ahmed, M. G., Choi, W. S., Elkholy, A. & Hanumolu, P. K., Jan 1 2020, (Accepted/In press) In : IEEE Journal of Solid-State Circuits.

Research output: Contribution to journalArticle

A Low-Noise Frequency Synthesizer Using Multiphase Generation and Combining Techniques

Khashaba, A., Elkholy, A., Megawer, K. M., Ahmed, M. G. & Hanumolu, P. K., Mar 2020, In : IEEE Journal of Solid-State Circuits. 55, 3, p. 592-601 10 p., 8903272.

Research output: Contribution to journalArticle

2019

18.5 A 54MHz Crystal Oscillator with 30× 18.5 Start-Up Time Reduction Using 2-Step Injection in 65nm CMOS

Megawer, K. M., Pal, N., Elkholy, A., Ahmed, M. G., Khashaba, A., Griffith, D. & Hanumolu, P. K., Mar 6 2019, 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019. Institute of Electrical and Electronics Engineers Inc., p. 302-304 3 p. 8662403. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 2019-February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

34-GBD linear transimpedance amplifier for 200-Gb/s DP-16-QAM optical coherent receivers

Ahmed, M. G., Huynh, T. N., Williams, C., Wang, Y., Hanumolu, P. K. & Rylyakov, A., Mar 2019, In : IEEE Journal of Solid-State Circuits. 54, 3, p. 834-844 11 p., 8570782.

Research output: Contribution to journalArticle

A 0.016 mm2 0.26-μ W/MHz 60-240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS

Zhu, J., Choi, W. S. & Hanumolu, P. K., Aug 2019, In : IEEE Journal of Solid-State Circuits. 54, 8, p. 2186-2194 9 p., 8723106.

Research output: Contribution to journalArticle

A 15-Gb/s sub-baud-rate digital CDR

Kim, D., Choi, W. S., Elkholy, A., Kenney, J. & Hanumolu, P. K., Mar 2019, In : IEEE Journal of Solid-State Circuits. 54, 3, p. 685-695 11 p., 8599124.

Research output: Contribution to journalArticle

A 2.5-5.75-GHz Ring-Based Injection-Locked Clock Multiplier with Background-Calibrated Reference Frequency Doubler

Elkholy, A., Coombs, D., Nandwana, R. K., Elmallah, A. & Hanumolu, P. K., Jul 2019, In : IEEE Journal of Solid-State Circuits. 54, 7, p. 2049-2058 10 p., 8691469.

Research output: Contribution to journalArticle

A 5GHz 245fsrms 8mW Ring Oscillator-based Digital Frequency Synthesizer

Khashaba, A., Elkholy, A., Megawer, K. M., Ahmed, M. & Hanumolu, P. K., Apr 2019, 2019 IEEE Custom Integrated Circuits Conference, CICC 2019. Institute of Electrical and Electronics Engineers Inc., 8780384. (Proceedings of the Custom Integrated Circuits Conference; vol. 2019-April).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A 6 μ W ±50 ppm/°C ±1500 ppm/V 1.5 MHz RC oscillator using self-regulation

Wang, T., Griffith, D., Ahmed, M. G., Zhu, J., Wei, D., Elkholy, A., Elmallah, A. & Hanumolu, P. K., Aug 2019, In : IEEE Transactions on Circuits and Systems II: Express Briefs. 66, 8, p. 1297-1301 5 p., 8556499.

Research output: Contribution to journalArticle

A Fast Startup CMOS Crystal Oscillator Using Two-Step Injection

Megawer, K. M., Pal, N., Elkholy, A., Ahmed, M. G., Khashaba, A., Griffith, D. & Hanumolu, P. K., Dec 2019, In : IEEE Journal of Solid-State Circuits. 54, 12, p. 3257-3268 12 p., 8827914.

Research output: Contribution to journalArticle

Design of crystal-oscillator frequency quadrupler for low-jitter clock multipliers

Megawer, K. M., Elkholy, A., Gamal Ahmed, M., Elmallah, A. & Kumar Hanumolu, P., Jan 2019, In : IEEE Journal of Solid-State Circuits. 54, 1, p. 65-74 10 p., 8486730.

Research output: Contribution to journalArticle

Message from the Incoming Editor-in-Chief

Hanumolu, P. K., Aug 2019, In : IEEE Journal of Solid-State Circuits. 54, 8, 1 p., 8769995.

Research output: Contribution to journalEditorial

2018

A 0.45-0.7 v 1-6 Gb/s 0.29-0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation

Choi, W. S., Shu, G., Talegaonkar, M., Liu, Y., Wei, D., Benini, L. & Hanumolu, P. K., Mar 2018, In : IEEE Journal of Solid-State Circuits. 53, 3, p. 884-895 12 p.

Research output: Contribution to journalArticle

A 1.6ps peak-INL 5.3ns range two-step digital-to-time converter in 65nm CMOS

Elmallah, A., Ahmed, M. G., Elkholy, A., Choi, W. S. & Hanumolu, P. K., May 9 2018, 2018 IEEE Custom Integrated Circuits Conference, CICC 2018. Institute of Electrical and Electronics Engineers Inc., p. 1-4 4 p. (2018 IEEE Custom Integrated Circuits Conference, CICC 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A 10-Gb/s/ch, 0.6-pJ/bit/mm Power Scalable Rapid-ON/OFF Transceiver for On-Chip Energy Proportional Interconnects

Wei, D., Anand, T., Shu, G., Schutt-Ainé, J. E. & Hanumolu, P. K., Mar 2018, In : IEEE Journal of Solid-State Circuits. 53, 3, p. 873-883 11 p.

Research output: Contribution to journalArticle

A 10-MHz 2-800-mA 0.5-1.5-V 90% Peak Efficiency Time-Based Buck Converter with Seamless Transition between PWM/PFM Modes

Kim, S. J., Choi, W. S., Pilawa-Podgurski, R. & Hanumolu, P. K., Mar 2018, In : IEEE Journal of Solid-State Circuits. 53, 3, p. 814-824 11 p.

Research output: Contribution to journalArticle

A 12-Gb/s -16.8-dBm OMA Sensitivity 23-mW Optical Receiver in 65-nm CMOS

Ahmed, M. G., Talegaonkar, M., Elkholy, A., Shu, G., Elmallah, A., Rylyakov, A. & Hanumolu, P. K., Feb 2018, In : IEEE Journal of Solid-State Circuits. 53, 2, p. 445-457 13 p., 8074728.

Research output: Contribution to journalArticle

A 15Gb/s 1.9pJ/bit sub-baud-rate digital CDR

Kim, D., Choi, W. S., Elkholy, A., Kenney, J. & Hanumolu, P. K., May 9 2018, 2018 IEEE Custom Integrated Circuits Conference, CICC 2018. Institute of Electrical and Electronics Engineers Inc., p. 1-4 4 p. (2018 IEEE Custom Integrated Circuits Conference, CICC 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A 5GHz 370fsrms 6.5mW clock multiplier using a crystal-oscillator frequency quadrupler in 65nm CMOS

Megawer, K. M., Elkholy, A., Coombs, D., Ahmed, M. G., Elmallah, A. & Hanumolu, P. K., Mar 8 2018, 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018. Institute of Electrical and Electronics Engineers Inc., p. 392-394 3 p. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 61).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A 6.75-8.25-GHz -250-dB FoM Rapid ON/OFF Fractional-N Injection-Locked Clock Multiplier

Elkholy, A., Elmallah, A., Ahmed, M. G. & Hanumolu, P. K., Jun 2018, In : IEEE Journal of Solid-State Circuits. 53, 6, p. 1818-1829 12 p.

Research output: Contribution to journalArticle

A modulo-based architecture for analog-to-digital conversion

Ordentlich, O., Tabak, G., Hanumolu, P. K., Singer, A. C. & Wornell, G. W., Oct 2018, In : IEEE Journal on Selected Topics in Signal Processing. 12, 5, p. 825-840 16 p., 8425696.

Research output: Contribution to journalArticle

Guaranteeing local differential privacy on ultra-low-power systems

Choi, W. S., Tomei, M., Vicarte, J. R. S., Hanumolu, P. K. & Kumar, R., Jul 19 2018, Proceedings - 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture, ISCA 2018. Institute of Electrical and Electronics Engineers Inc., p. 561-574 14 p. 8416855. (Proceedings - International Symposium on Computer Architecture).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers

Elkholy, A., Saxena, S., Shu, G., Elshazly, A. & Hanumolu, P. K., Jun 2018, In : IEEE Journal of Solid-State Circuits. 53, 6, p. 1806-1817 12 p.

Research output: Contribution to journalArticle

Time-Based PWM controller for fully integrated high speed switching DC-DC converters-an alternative to conventional analog and digital controllers

Khan, Q. A., Kim, S. J. & Hanumolu, P. K., Mar 27 2018, Proceedings - 31st International Conference on VLSI Design, VLSID 2018 - Held concurrently with 17th International Conference on Embedded Systems, ES 2018. IEEE Computer Society, p. 226-231 6 p. (Proceedings of the IEEE International Conference on VLSI Design; vol. 2018-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2017

A 0.0021 mm2 1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS

Zhu, J., Nandwana, R. K., Shu, G., Elkholy, A., Kim, S. J. & Hanumolu, P. K., Jan 2017, In : IEEE Journal of Solid-State Circuits. 52, 1, p. 8-20 13 p., 7564468.

Research output: Contribution to journalArticle

A 0.7V time-based inductor for fully integrated low bandwidth filter applications

Salz, B., Talegaonkar, M., Shu, G., Elmallah, A., Nandwana, R., Sahoo, B. & Hanumolu, P. K., Jul 26 2017, 38th Annual Custom Integrated Circuits Conference: A Showcase for Integrated Circuit Design in Silicon Hills, CICC 2017. Institute of Electrical and Electronics Engineers Inc., 7993606. (Proceedings of the Custom Integrated Circuits Conference; vol. 2017-April).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A 10MHz 2mA-800mA 0.5V-1.5V 90% peak efficiency time-based buck converter with seamless transition between PWM/PFM modes

Kim, S. J., Choi, W., Pilawa-Podgurski, R. & Hanumolu, P. K., Jul 26 2017, 38th Annual Custom Integrated Circuits Conference: A Showcase for Integrated Circuit Design in Silicon Hills, CICC 2017. Institute of Electrical and Electronics Engineers Inc., 7993619. (Proceedings of the Custom Integrated Circuits Conference; vol. 2017-April).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A 1-to-2048 fully-integrated cascaded digital frequency synthesizer for low frequency reference clocks using scrambling TDC

Nandwana, R. K., Saxena, S., Elshazly, A., Mayaram, K. & Hanumolu, P. K., Feb 2017, In : IEEE Transactions on Circuits and Systems I: Regular Papers. 64, 2, p. 283-295 13 p., 7731190.

Research output: Contribution to journalArticle

A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS

Coombs, D., Elkholy, A., Nandwana, R. K., Elmallah, A. & Hanumolu, P. K., Mar 2 2017, 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017. Fujino, L. C. (ed.). Institute of Electrical and Electronics Engineers Inc., p. 152-153 2 p. 7870306. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 60).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver

Saxena, S., Shu, G., Nandwana, R. K., Talegaonkar, M., Elkholy, A., Anand, T., Choi, W. S. & Hanumolu, P. K., May 2017, In : IEEE Journal of Solid-State Circuits. 52, 5, p. 1399-1411 13 p., 7890481.

Research output: Contribution to journalArticle

A 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS

Nandwana, R. K., Saxena, S., Elkholy, A., Talegaonkar, M., Zhu, J., Choi, W. S., Elmallah, A. & Hanumolu, P. K., Mar 2 2017, 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017. Fujino, L. C. (ed.). Institute of Electrical and Electronics Engineers Inc., p. 492-493 2 p. 7870476. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 60).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A 45-75MHz 197-452μW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOS

Zhu, J., Mahalley, M., Shu, G., Choi, W. S., Nandwana, R. K., Elkholy, A., Sahoo, B. & Hanumolu, P. K., Jul 26 2017, 38th Annual Custom Integrated Circuits Conference: A Showcase for Integrated Circuit Design in Silicon Hills, CICC 2017. Institute of Electrical and Electronics Engineers Inc., 7993679. (Proceedings of the Custom Integrated Circuits Conference; vol. 2017-April).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS

Talegaonkar, M., Anand, T., Elkholy, A., Elshazly, A., Nandwana, R. K., Saxena, S., Young, B., Choi, W. S. & Hanumolu, P. K., Sep 2017, In : IEEE Journal of Solid-State Circuits. 52, 9, p. 2306-2320 15 p., 7999180.

Research output: Contribution to journalArticle

A 94.2%-peak-efficiency 1.53A direct-battery-hook-up hybrid Dickson switched-capacitor DC-DC converter with wide continuous conversion ratio in 65nm CMOS

Liu, W. C., Assem, P., Lei, Y., Hanumolu, P. K. & Pilawa-Podgurski, R., Mar 2 2017, 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017. Fujino, L. C. (ed.). Institute of Electrical and Electronics Engineers Inc., p. 182-183 2 p. 7870321. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 60).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Time-based ΔΣADCs

Hanumolu, P. K., Jul 26 2017, 38th Annual Custom Integrated Circuits Conference: A Showcase for Integrated Circuit Design in Silicon Hills, CICC 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2017-April. 7993722

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Understanding and Optimizing Power Consumption in Memory Networks

Jian, X., Hanumolu, P. K. & Kumar, R., May 5 2017, Proceedings - 2017 IEEE 23rd Symposium on High Performance Computer Architecture, HPCA 2017. IEEE Computer Society, p. 229-240 12 p. 7920828

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2016

A 0.0021mm2 1.82mW 2.2GHz PLL using time-based integral control in 65nm CMOS

Zhu, J., Nandwana, R. K., Shu, G., Elkholy, A., Kim, S. J. & Hanumolu, P. K., Feb 23 2016, 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016. Institute of Electrical and Electronics Engineers Inc., p. 338-340 3 p. 7418045. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 59).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS

Shu, G., Choi, W. S., Saxena, S., Kim, S. J., Talegaonkar, M., Nandwana, R., Elkholy, A., Wei, D., Nandi, T. & Hanumolu, P. K., Feb 23 2016, 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016. Institute of Electrical and Electronics Engineers Inc., p. 398-399 2 p. 7418075. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 59).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL with Extended Range Multi-Modulus Divider

Elkholy, A., Saxena, S., Nandwana, R. K., Elshazly, A. & Hanumolu, P. K., Aug 2016, In : IEEE Journal of Solid-State Circuits. 51, 8, p. 1771-1784 14 p., 7489022.

Research output: Contribution to journalArticle

A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition

Shu, G., Choi, W. S., Saxena, S., Talegaonkar, M., Anand, T., Elkholy, A., Elshazly, A. & Hanumolu, P. K., Feb 1 2016, In : IEEE Journal of Solid-State Circuits. 51, 2, p. 428-439 12 p., 7362125.

Research output: Contribution to journalArticle

A 6.75-to-8.25GHz, 250fsrms-integrated-jitter 3.25mW rapid on/off PVT-insensitive fractional-N injection-locked clock multiplier in 65nm CMOS

Elkholy, A., Elmallah, A., Elzeftawi, M., Chang, K. & Hanumolu, P. K., Feb 23 2016, 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016. Institute of Electrical and Electronics Engineers Inc., p. 192-193 2 p. 7417972. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 59).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A VCO Based Highly Digital Temperature Sensor with 0.034 °c/mV Supply Sensitivity

Anand, T., Makinwa, K. A. A. & Hanumolu, P. K., Nov 2016, In : IEEE Journal of Solid-State Circuits. 51, 11, p. 2651-2663 13 p.

Research output: Contribution to journalArticle

Digital Clock and Data Recovery Circuits for Optical Links

Shu, G., Choi, W. S. & Hanumolu, P. K., Nov 21 2016, 2016 IEEE Compound Semiconductor Integrated Circuit Symposium, CSICS 2016 - Technical Digest. Institute of Electrical and Electronics Engineers Inc., 7751036. (Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC; vol. 2016-November).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2015

A 0.45-to-0.7V 1-to-6Gb/S 0.29-to-0.58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS

Choi, W. S., Shu, G., Talegaonkar, M., Liu, Y., Wei, D., Benini, L. & Hanumolu, P. K., Mar 17 2015, 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., p. 66-67 2 p. 7062928. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 58).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A1.8V 30-to-70MHz 87% peak-efficiency 0.32mm2 4-phase time-based buck converter consuming 3μA/MHz quiescent current in 65nm CMOS

Kim, S. J., Nandwana, R. K., Khan, Q., Pilawa-Podgurski, R. & Hanumolu, P. K., Mar 17 2015, 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., p. 216-217 2 p. 7063003. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 58).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS

Saxena, S., Shu, G., Nandwana, R. K., Talegaonkar, M., Elkholy, A., Anand, T., Kim, S. J., Choi, W. S. & Hanumolu, P. K., Aug 31 2015, 2015 Symposium on VLSI Circuits, VLSI Circuits 2015. Institute of Electrical and Electronics Engineers Inc., p. C352-C353 7231320. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; vol. 2015-August).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC

Elkholy, A., Anand, T., Choi, W. S., Elshazly, A. & Hanumolu, P. K., Apr 1 2015, In : IEEE Journal of Solid-State Circuits. 50, 4, p. 867-881 15 p., 7027236.

Research output: Contribution to journalArticle

A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter

Elkholy, A., Saxena, S., Nandwana, R. K., Elshazly, A. & Hanumolu, P. K., Nov 25 2015, 2015 IEEE Custom Integrated Circuits Conference, CICC 2015. Institute of Electrical and Electronics Engineers Inc., 7338376. (Proceedings of the Custom Integrated Circuits Conference; vol. 2015-November).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A 4-Phase 30-70 MHz Switching Frequency Buck Converter Using a Time-Based Compensator

Kim, S. J., Nandwana, R. K., Khan, Q., Pilawa Podgurski, R. C. N. & Hanumolu, P. K., Dec 2015, In : IEEE Journal of Solid-State Circuits. 50, 12, p. 2814-2824 11 p., 7182789.

Research output: Contribution to journalArticle