If you made any changes in Pure, your changes will be visible here soon.

Fingerprint Fingerprint is based on mining the text of the expert's scholarly documents to create an index of weighted terms, which defines the key subjects of each individual researcher.

  • 3 Similar Profiles
Phase locked loops Engineering & Materials Science
Jitter Engineering & Materials Science
Clocks Engineering & Materials Science
Variable frequency oscillators Engineering & Materials Science
Bandwidth Engineering & Materials Science
Electric potential Engineering & Materials Science
Clock and data recovery circuits (CDR circuits) Engineering & Materials Science
Calibration Engineering & Materials Science

Network Recent external collaboration on country level. Dive into details by clicking on the dots.

Research Output 2003 2019

  • 92 Conference contribution
  • 77 Article
  • 6 Conference article
  • 5 Editorial

18.5 A 54MHz Crystal Oscillator with 30× 18.5 Start-Up Time Reduction Using 2-Step Injection in 65nm CMOS

Megawer, K. M., Pal, N., Elkholy, A., Ahmed, M. G., Khashaba, A., Griffith, D. & Hanumolu, P. K., Mar 6 2019, 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019. Institute of Electrical and Electronics Engineers Inc., p. 302-304 3 p. 8662403. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 2019-February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Crystal oscillators
Crystal resonators
Phase noise
Resonators
Communication systems

34-GBD linear transimpedance amplifier for 200-Gb/s DP-16-QAM optical coherent receivers

Ahmed, M. G., Huynh, T. N., Williams, C., Wang, Y., Hanumolu, P. K. & Rylyakov, A., Mar 2019, In : IEEE Journal of Solid-State Circuits. 54, 3, p. 834-844 11 p., 8570782.

Research output: Contribution to journalArticle

Optical receivers
Operational amplifiers
Quadrature amplitude modulation
Telecommunication links
Optical communication

A 0.016 mm2 0.26-μ W/MHz 60-240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS

Zhu, J., Choi, W. S. & Hanumolu, P. K., Aug 2019, In : IEEE Journal of Solid-State Circuits. 54, 8, p. 2186-2194 9 p., 8723106.

Research output: Contribution to journalArticle

Phase locked loops
Clocks
Frequency stability
Relaxation oscillators
Controllers

A 15-Gb/s sub-baud-rate digital CDR

Kim, D., Choi, W. S., Elkholy, A., Kenney, J. & Hanumolu, P. K., Mar 2019, In : IEEE Journal of Solid-State Circuits. 54, 3, p. 685-695 11 p., 8599124.

Research output: Contribution to journalArticle

Clocks
Recovery
Jitter
Clock and data recovery circuits (CDR circuits)
Equalizers

A 2.5-5.75-GHz Ring-Based Injection-Locked Clock Multiplier with Background-Calibrated Reference Frequency Doubler

Elkholy, A., Coombs, D., Nandwana, R. K., Elmallah, A. & Hanumolu, P. K., Jul 2019, In : IEEE Journal of Solid-State Circuits. 54, 7, p. 2049-2058 10 p., 8691469.

Research output: Contribution to journalArticle

Frequency doublers
Clocks
Jitter
Spurious signal noise
Bandwidth