1985 …2019

Research output per year

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Research Output

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2019

DtCraft: A High-Performance Distributed Execution Engine at Scale

Huang, T. W., Lin, C. X. & Wong, M. D. F., Jun 2019, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 38, 6, p. 1070-1083 14 p., 8355904.

Research output: Contribution to journalArticle

2016

PolyPUF: Physically Secure Self-Divergence

Konigsmark, S. T. C., Chen, D. & Wong, M. D. F., Jul 2016, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 35, 7, p. 1053-1066 14 p., 7293632.

Research output: Contribution to journalArticle

UI-Timer 1.0: An Ultrafast Path-Based Timing Analysis Algorithm for CPPR

Huang, T. W. & Wong, M. D. F., Nov 2016, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 35, 11, p. 1862-1875 14 p., 7400988.

Research output: Contribution to journalArticle

2015

Accelerating aerial image simulation using improved CPU/GPU collaborative computing

Zhang, F., Hu, C., Wu, P. C., Zhang, H. & Wong, M. D. F., Jan 1 2015, In : Computers and Electrical Engineering. 46, p. 176-189 14 p.

Research output: Contribution to journalArticle

2014

ICCAD roundtable the many challenges of triple patterning [ICCAD Roundtable]

Joyner, W., Kawa, J., Liebmann, L., Pan, D. Z., Wong, M. & Yeh, D., Aug 2014, In : IEEE Design and Test. 31, 4, p. 52-58 7 p., 6874606.

Research output: Contribution to journalArticle

2013

A routing algorithm for graphene nanoribbon circuit

Yan, T., Ma, Q., Chilstedt, S., Wong, M. D. F. & Chen, D., Oct 1 2013, In : ACM Transactions on Design Automation of Electronic Systems. 18, 4, 61.

Research output: Contribution to journalArticle

2012

Advances in PCB routing

Yan, T., Ma, Q. & Wong, M. D. F., Aug 17 2012, In : IPSJ Transactions on System LSI Design Methodology. 5, p. 14-22 9 p.

Research output: Contribution to journalArticle

A practical low-power nonregular interconnect design with manufacturing for design approach

Zhang, H., Wong, M. D. F., Chao, K. Y. & Deng, L., May 15 2012, In : IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 2, 2, p. 322-332 11 p., 6198293.

Research output: Contribution to journalArticle

Correctly model the diagonal capacity in escape routing

Yan, T. & Wong, M. D. F., Feb 1 2012, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 31, 2, p. 285-293 9 p., 6132657.

Research output: Contribution to journalArticle

2011

A new strategy for simultaneous escape based on boundary routing

Luo, L., Yan, T., Ma, Q., Wong, M. D. F. & Shibuya, T., Feb 1 2011, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30, 2, p. 205-214 10 p., 5689348.

Research output: Contribution to journalArticle

Thermal-driven analog placement considering device matching

Lin, M. P. H., Zhang, H., Wong, M. D. F. & Chang, Y. W., Mar 1 2011, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30, 3, p. 325-336 12 p., 5715604.

Research output: Contribution to journalArticle

2010

A routing approach to reduce glitches in low power FPGAs

Dinh, Q., Chen, D. & Wong, M. D. F., Feb 1 2010, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 29, 2, p. 235-240 6 p., 5395747.

Research output: Contribution to journalArticle

2009

Archer: A history-based global routing algorithm

Ozdal, M. M. & Wong, M. D. F., Jan 1 2009, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 28, 1, p. 528-540 13 p.

Research output: Contribution to journalArticle

Archer: A history-based global routing algorithm

Ozdal, M. M. & Wong, M. D. F., Apr 1 2009, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 28, 4, p. 528-540 13 p., 4802223.

Research output: Contribution to journalArticle

BSG-route: A length-constrained routing scheme for general planar topology

Yan, T. & Wong, M. D. F., Nov 1 2009, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 28, 11, p. 1679-1690 12 p., 5290341.

Research output: Contribution to journalArticle

Incremental improvement of voltage assignment

Wu, H. & Wong, M. D. F., Jan 1 2009, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 28, 1, p. 217-230 14 p.

Research output: Contribution to journalArticle

Incremental improvement of voltage assignment

Wu, H. & Wong, M. D. F., Feb 1 2009, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 28, 2, p. 217-230 14 p., 4757334.

Research output: Contribution to journalArticle

2008

DDBDD: Delay-driven BPD synthesis for FPGAs

Cheng, L., Chen, D. & Wong, M. D. F., Jul 1 2008, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 27, 7, p. 1203-1213 11 p., 4544856.

Research output: Contribution to journalArticle

Fast dummy-fill density analysis with coupling constraints

Xiang, H., Deng, L., Puri, R., Chao, K. Y. & Wong, M. D. F., Apr 1 2008, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 27, 4, p. 633-642 10 p., 4475260.

Research output: Contribution to journalArticle

Is your layout-density verification exact?A fast exact deep submicrometer density calculation algorithm

Xiang, H., Chao, K. Y., Puri, R. & Wong, M. D. F., Apr 1 2008, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 27, 4, p. 621-632 12 p., 4475259.

Research output: Contribution to journalArticle

Optimal routing algorithms for rectilinear pin clusters in high-density multichip modules

Ozdal, M. M., Wong, M. D. F. & Honsinger, P. S., Sep 1 2008, In : ACM Transactions on Design Automation of Electronic Systems. 13, 4, 68.

Research output: Contribution to journalArticle

Postplacement voltage assignment under performance constraints

Wu, H., Wong, M. D. F. & Gosti, W., Jul 1 2008, In : ACM Transactions on Design Automation of Electronic Systems. 13, 3

Research output: Contribution to journalArticle

Simultaneous escape-routing algorithms for via minimization of high-speed boards

Ozdal, M. M., Wong, M. D. F. & Honsinger, P. S., Jan 1 2008, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 27, 1, p. 84-94 11 p.

Research output: Contribution to journalArticle

2007

Placement-proximity-based voltage island grouping under performance requirement

Wu, H., Wong, M. D. F., Liu, I. M. & Wang, Y., Jul 1 2007, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 26, 7, p. 1256-1269 14 p., 4237245.

Research output: Contribution to journalArticle

2006

Algorithms for simultaneous escape routing and layer assignment of dense PCBs

Ozdal, M. M. & Wong, M. D. F., Aug 1 2006, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 25, 8, p. 1510-1522 13 p., 1637740.

Research output: Contribution to journalArticle

An ECO routing algorithm for eliminating coupling-capacitance violations

Xiang, H., Chao, K. Y. & Wong, M. D. F., Sep 1 2006, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 25, 9, p. 1754-1761 8 p., 1673749.

Research output: Contribution to journalArticle

Floorplan design for multimillion gate FPGAs

Cheng, L. & Wong, M. D. F., Dec 1 2006, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 25, 12, p. 2795-2805 11 p.

Research output: Contribution to journalArticle

I/O clustering in design cost and performance optimization for flip-chip design

Chen, H. M., Liu, I. M. & Wong, M. D. F., Nov 1 2006, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 25, 11, p. 2552-2556 5 p., 1715437.

Research output: Contribution to journalArticle

Minimizing wire length in floorplanning

Tang, X., Tian, R. & Wong, M. D. F., Sep 1 2006, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 25, 9, p. 1744-1753 10 p., 1673748.

Research output: Contribution to journalArticle

Temperature-aware placement for SOCs

Tsai, J. L., Chen, C. C. P., Chen, G., Goplen, B., Qian, H., Zhan, Y., Kang, S. M., Wong, M. D. F. & Sapatnekar, S. S., Aug 1 2006, In : Proceedings of the IEEE. 94, 8, p. 1502-1517 16 p.

Research output: Contribution to journalArticle

Two-layer bus routing for high-speed printed circuit boards

Ozdal, M. M. & Wong, M. D. F., Jan 1 2006, In : ACM Transactions on Design Automation of Electronic Systems. 11, 1, p. 213-227 15 p.

Research output: Contribution to journalArticle

2005

An algorithm for integrated pin assignment and buffer planning

Xiang, H., Tang, X. & Wong, M. D. F., Dec 1 2005, In : ACM Transactions on Design Automation of Electronic Systems. 10, 3, p. 561-572 12 p.

Research output: Contribution to journalArticle

Simultaneous power supply planning and noise avoidance in floorplan design

Chen, H. M., Huang, L. D., Liu, I. M. & Wong, M. D. F., Apr 1 2005, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 24, 4, p. 578-586 9 p.

Research output: Contribution to journalArticle

2004

A Polynomial Time-Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem

Huang, L. D., Tang, X., Xiang, H., Wong, M. D. F. & Liu, I. M., Jan 1 2004, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 23, 1, p. 141-147 7 p.

Research output: Contribution to journalArticle

Bus-driven floorplanning

Xiang, H., Tang, X. & Wong, M. D. F., Nov 1 2004, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 23, 11, p. 1522-1530 9 p.

Research output: Contribution to journalArticle

2003

Analysis of FPGA/FPIC switch modules

Chang, Y. W., Zhu, K., Wu, G. M., Wong, M. D. F. & Wong, C. K., Jan 1 2003, In : ACM Transactions on Design Automation of Electronic Systems. 8, 1, p. 11-37 27 p.

Research output: Contribution to journalArticle

Design hierarchy-guided multilevel circuit partitioning

Cheon, Y. & Wong, M. D. F., Apr 1 2003, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 22, 4, p. 420-427 8 p.

Research output: Contribution to journalArticle

Maze routing with buffer insertion under transition time constraints

Huang, L. D., Lai, M., Wong, D. F. & Gao, Y., Jan 1 2003, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 22, 1, p. 91-96 6 p.

Research output: Contribution to journalArticle

Min-cost flow-based algorithm for simultaneous pin assignment and routing

Xiang, H., Tang, X. & Wong, M. D. F., Jul 1 2003, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 22, 7, p. 870-878 9 p.

Research output: Contribution to journalArticle

Timing-driven routing for FPGAs based on Lagrangian relaxation

Lee, S. & Wong, M. D. F., Apr 1 2003, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 22, 4, p. 506-511 6 p.

Research output: Contribution to journalArticle

2002

Maze routing with buffer insertion and wiresizing

Lai, M. & Wong, D. F., Oct 1 2002, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 21, 10, p. 1205-1208 4 p.

Research output: Contribution to journalArticle

Optimal wire-sizing function under the Elmore delay model with bounded wire sizes

Lee, Y. M., Chen, C. C. P. & Wong, D. F., Nov 1 2002, In : IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications. 49, 11, p. 1671-1677 7 p.

Research output: Contribution to journalArticle

Simultaneous buffer-sizing and wire-sizing for clock trees based on lagrangian relaxation

Lee, Y. M., Chen, C. C. P., Chang, Y. W. & Wong, D. F., Jan 1 2002, In : VLSI Design. 15, 3, p. 587-594 8 p.

Research output: Contribution to journalArticle