1985 …2019
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Research Output 1985 2019

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Paper
2004

An ECO algorithm for eliminating crosstalk violations

Xiang, H., Chao, K. Y. & Wong, M. D. F., Jun 28 2004, p. 41-46. 6 p.

Research output: Contribution to conferencePaper

Crosstalk
Wire

On handling arbitrary rectilinear shape constraint

Tang, X. & Wong, M. D. F., Jun 1 2004, p. 38-41. 4 p.

Research output: Contribution to conferencePaper

Simulated annealing
2003

Explicit gate delay model for timing evaluation

Shao, M., Wong, M. D. F., Cao, H., Gao, Y., Yuan, L. P., Huang, L. D. & Lee, S., Jul 28 2003, p. 32-38. 7 p.

Research output: Contribution to conferencePaper

Resistors
Poles
Capacitance
Switches
Networks (circuits)

Wire type assignment for FPGA routing

Lee, S., Xiang, H., Wong, M. D. F. & Sun, R. Y., Jul 17 2003, p. 61-67. 7 p.

Research output: Contribution to conferencePaper

Field programmable gate arrays (FPGA)
Wire
Costs
Experiments
2002

Design hierarchy guided multilevel circuit partitioning

Cheon, Y. & Wong, D. F., Jan 1 2002, p. 30-35. 6 p.

Research output: Contribution to conferencePaper

Networks (circuits)
Coarsening
Product design

Incremental reconfiguration of multi-FPGA systems

Lee, K. K. & Wong, M. D. F., Jan 1 2002, p. 206-213. 8 p.

Research output: Contribution to conferencePaper

Field programmable gate arrays (FPGA)
Trees (mathematics)
Approximation algorithms
Heuristic algorithms
Topology

Timing-driven routing for FPGAs based on Lagrangian relaxation

Lee, S. & Wong, D. F., Jan 1 2002, p. 176-181. 6 p.

Research output: Contribution to conferencePaper

Field programmable gate arrays (FPGA)
Networks (circuits)
Routers
Routing algorithms
Cost functions
2001

Dummy feature placement for chemical-mechanical polishing uniformity in a shallow trench isolation process

Tian, R., Tang, X. & Wong, M. D. F., Jan 1 2001, p. 118-123. 6 p.

Research output: Contribution to conferencePaper

Chemical mechanical polishing
Nonlinear programming
Topography
Compaction
2000

Planning buffer locations by network flows

Tang, X. & Wong, D. F., Jan 1 2000, p. 180-185. 6 p.

Research output: Contribution to conferencePaper

Planning
Networks (circuits)
Costs
Polynomials

Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion

Liu, I. M., Chou, T. L., Aziz, A. & Wong, D. F., Jan 1 2000, p. 33-38. 6 p.

Research output: Contribution to conferencePaper

Clocks
Wire
Merging
Processing
Experiments
1999

Circuit partitioning for dynamically reconfigurable FPGAs

Liu, H. & Wong, D. F., Jan 1 1999, p. 187-194. 8 p.

Research output: Contribution to conferencePaper

Field programmable gate arrays (FPGA)
Networks (circuits)
Scheduling
Communication
Costs

Efficient buffer insertion algorithm for large networks based on Lagrangian relaxation

Liu, I. M., Aziz, A., Wong, D. F. & Zhou, H., Dec 1 1999, p. 210-215. 6 p.

Research output: Contribution to conferencePaper

Topology
Costs

Slicing floorplans with range constraint

Young, F. Y. & Wong, D. F., Jan 1 1999, p. 97-102. 6 p.

Research output: Contribution to conferencePaper

1998

Circuit partitioning with complex resource constraints in FPGAs

Liu, H., Zhu, K. & Wong, M. D. F., Jan 1 1998, p. 77-84. 8 p.

Research output: Contribution to conferencePaper

Field programmable gate arrays (FPGA)
Networks (circuits)
Logic design

Greedy wire-sizing is linear time

Chu, C. C. N. & Wong, D. F., Jan 1 1998, p. 39-44. 6 p.

Research output: Contribution to conferencePaper

Wire

Performance-driven board-level routing for FPGA-based logic emulation

Mak, W. K. & Wong, M. D. F., Dec 1 1998, p. 199-201. 3 p.

Research output: Contribution to conferencePaper

Field programmable gate arrays (FPGA)
Routing algorithms
1997

Closed form solution to simultaneous buffer insertion/sizing and wire sizing

Chu, C. C. N. & Wong, D. F., Jan 1 1997, p. 192-197. 6 p.

Research output: Contribution to conferencePaper

Wire

Clustering and load balancing for buffered clock tree synthesis

Mehta, A. D., Chen, Y. P., Menezes, N., Wong, D. F. & Pileggi, L. T., Dec 1 1997, p. 217-223. 7 p.

Research output: Contribution to conferencePaper

Resource allocation
Clocks
Wire
Clustering algorithms
Capacitance

Crosstalk-constrained maze routing based on Lagrangian relaxation

Zhou, H. & Wong, D. F., Dec 1 1997, p. 628-633. 6 p.

Research output: Contribution to conferencePaper

Crosstalk
Wire
VLSI circuits
Heuristic algorithms
Networks (circuits)

How good are slicing floorplans?

Young, F. Y. & Wong, D. F., Jan 1 1997, p. 144-149. 6 p.

Research output: Contribution to conferencePaper

Matrix synthesis approach to thermal placement

Chu, C. C. N. & Wong, D. F., Jan 1 1997, p. 163-168. 6 p.

Research output: Contribution to conferencePaper

Heat problems
Combinatorial optimization
Approximation algorithms
Electric wiring
Computational complexity
1996

Multiplexor network generation in high level synthesis

Fang, Y. M. & Wong, D. F., Dec 1 1996, p. 78-83. 6 p.

Research output: Contribution to conferencePaper

High level synthesis

Universal logic modules for series-parallel functions

Thakur, S. & Wong, D. F., Jan 1 1996, p. 31-37. 7 p.

Research output: Contribution to conferencePaper

Trees (mathematics)
Field programmable gate arrays (FPGA)
Transistors
Networks (circuits)
Logic Synthesis

Universal switch-module design for symmetric-array-based FPGAs

Chang, Y. W., Wong, D. F. & Wong, C. K., Jan 1 1996, p. 80-86. 7 p.

Research output: Contribution to conferencePaper

Field programmable gate arrays (FPGA)
Switches
1995

Design and analysis of FPGA/FPIC switch modules

Chang, Y. W., Wong, D. F. & Wong, C. K., Dec 1 1995, p. 394-401. 8 p.

Research output: Contribution to conferencePaper

Field programmable gate arrays (FPGA)
Switches
Heuristic algorithms
Experiments

FPGA global routing based on a new congestion metric

Chang, Y. W., Wong, D. F. & Wong, C. K., Dec 1 1995, p. 372-378. 7 p.

Research output: Contribution to conferencePaper

Field programmable gate arrays (FPGA)
Switches
Application specific integrated circuits
Routers
Experiments

Simultaneous area and delay minimum K-LUT mapping for K-exact networks

Thakur, S. & Wong, M. D. F., Dec 1 1995, p. 402-408. 7 p.

Research output: Contribution to conferencePaper

Table lookup
Polynomials
Field programmable gate arrays (FPGA)
1994

On retiming for FPGA logic module minimization

Chen, Y. P. & Wong, D. F., Dec 1 1994, p. 394-397. 4 p.

Research output: Contribution to conferencePaper

Flip flop circuits
Field programmable gate arrays (FPGA)
Sequential circuits