1985 …2019

Research output per year

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Research Output

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Paper
2004

An ECO algorithm for eliminating crosstalk violations

Xiang, H., Chao, K. Y. & Wong, M. D. F., Jun 28 2004, p. 41-46. 6 p.

Research output: Contribution to conferencePaper

On handling arbitrary rectilinear shape constraint

Tang, X. & Wong, M. D. F., Jun 1 2004, p. 38-41. 4 p.

Research output: Contribution to conferencePaper

2003

Explicit gate delay model for timing evaluation

Shao, M., Wong, M. D. F., Cao, H., Gao, Y., Yuan, L. P., Huang, L. D. & Lee, S., Jul 28 2003, p. 32-38. 7 p.

Research output: Contribution to conferencePaper

Wire type assignment for FPGA routing

Lee, S., Xiang, H., Wong, M. D. F. & Sun, R. Y., Jul 17 2003, p. 61-67. 7 p.

Research output: Contribution to conferencePaper

2002

Incremental reconfiguration of multi-FPGA systems

Lee, K. K. & Wong, M. D. F., Jan 1 2002, p. 206-213. 8 p.

Research output: Contribution to conferencePaper

Timing-driven routing for FPGAs based on Lagrangian relaxation

Lee, S. & Wong, D. F., Jan 1 2002, p. 176-181. 6 p.

Research output: Contribution to conferencePaper

2001

Dummy feature placement for chemical-mechanical polishing uniformity in a shallow trench isolation process

Tian, R., Tang, X. & Wong, M. D. F., Jan 1 2001, p. 118-123. 6 p.

Research output: Contribution to conferencePaper

2000
1999

Circuit partitioning for dynamically reconfigurable FPGAs

Liu, H. & Wong, D. F., Jan 1 1999, p. 187-194. 8 p.

Research output: Contribution to conferencePaper

Efficient buffer insertion algorithm for large networks based on Lagrangian relaxation

Liu, I. M., Aziz, A., Wong, D. F. & Zhou, H., Dec 1 1999, p. 210-215. 6 p.

Research output: Contribution to conferencePaper

Exact tree-based structural technology mapping algorithm for configurable logic blocks in FPGAs

Lee, K. K. & Wong, D. F., Dec 1 1999, p. 216-221. 6 p.

Research output: Contribution to conferencePaper

Slicing floorplans with range constraint

Young, F. Y. & Wong, D. F., Jan 1 1999, p. 97-102. 6 p.

Research output: Contribution to conferencePaper

1998

Circuit partitioning with complex resource constraints in FPGAs

Liu, H., Zhu, K. & Wong, D. F., Jan 1 1998, p. 77-84. 8 p.

Research output: Contribution to conferencePaper

Greedy wire-sizing is linear time

Chu, C. C. N. & Wong, D. F., Jan 1 1998, p. 39-44. 6 p.

Research output: Contribution to conferencePaper

1997

Channel segmentation design for symmetrical FPGAs

Mak, W. K. & Wong, D. F., Dec 1 1997, p. 496-501. 6 p.

Research output: Contribution to conferencePaper

Clustering and load balancing for buffered clock tree synthesis

Mehta, A. D., Chen, Y. P., Menezes, N., Wong, D. F. & Pileggi, L. T., Dec 1 1997, p. 217-223. 7 p.

Research output: Contribution to conferencePaper

Crosstalk-constrained maze routing based on Lagrangian relaxation

Zhou, H. & Wong, D. F., Dec 1 1997, p. 628-633. 6 p.

Research output: Contribution to conferencePaper

How good are slicing floorplans?

Young, F. Y. & Wong, D. F., Jan 1 1997, p. 144-149. 6 p.

Research output: Contribution to conferencePaper

Matrix synthesis approach to thermal placement

Chu, C. C. N. & Wong, D. F., Jan 1 1997, p. 163-168. 6 p.

Research output: Contribution to conferencePaper

1996

Multiplexor network generation in high level synthesis

Fang, Y. M. & Wong, D. F., Dec 1 1996, p. 78-83. 6 p.

Research output: Contribution to conferencePaper

Universal switch-module design for symmetric-array-based FPGAs

Chang, Y. W., Wong, D. F. & Wong, C. K., Jan 1 1996, p. 80-86. 7 p.

Research output: Contribution to conferencePaper

1995

Design and analysis of FPGA/FPIC switch modules

Chang, Y. W., Wong, D. F. & Wong, C. K., Dec 1 1995, p. 394-401. 8 p.

Research output: Contribution to conferencePaper

FPGA global routing based on a new congestion metric

Chang, Y. W., Wong, D. F. & Wong, C. K., Dec 1 1995, p. 372-378. 7 p.

Research output: Contribution to conferencePaper

Simultaneous area and delay minimum K-LUT mapping for K-exact networks

Thakur, S. & Wong, D. F., Dec 1 1995, p. 402-408. 7 p.

Research output: Contribution to conferencePaper

1994

Algorithms for a switch module routing problem

Thakur, S., Wong, D. F. & Muthukrishnan, S., Dec 1 1994, p. 265-270. 6 p.

Research output: Contribution to conferencePaper

On retiming for FPGA logic module minimization

Chen, Y. P. & Wong, D. F., Dec 1 1994, p. 394-397. 4 p.

Research output: Contribution to conferencePaper