1985 …2019
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Research Output 1985 2019

Filter
Conference contribution
2003

Floorplanning with power supply noise avoidance

Chen, H. M., Huang, L. D., Liu, I. M., Lai, M. & Wong, D. F., Jan 1 2003, Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc., p. 427-430 4 p. 1195053. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 2003-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Integrated circuits
Planning
Turnaround time
System-on-chip
2002

An algorithm for integrated pin assignment and buffer planning

Xiang, H., Tang, X. & Wong, M. D. F., 2002, Proceedings of the 39th Annual Design Automation Conference, DAC'02. p. 584-589 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Planning
Macros
Polynomials
Wire
Costs

Floorplanning with alignment and performance constraints

Tang, X. & Wong, D. F., Aug 31 2002, Proceedings of the 39th Annual Design Automation Conference, DAC'02. p. 848-853 6 p. (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Wire
Planning
2001

A fast and accurate delay estimation method for buffered interconnects

Gao, Y. & Wong, M. D. F., Jan 1 2001, Proceedings of the ASP-DAC 2001: Asia and South Pacific Design Automation Conference 2001. Institute of Electrical and Electronics Engineers Inc., p. 533-538 6 p. 913363. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 2001-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Wire
Capacitance
Transfer functions
SPICE
Threshold voltage

FAST-SP: A fast algorithm for block placement based on sequence pair

Tang, X. & Wong, D. F., Jan 1 2001, Proceedings of the ASP-DAC 2001: Asia and South Pacific Design Automation Conference 2001. Institute of Electrical and Electronics Engineers Inc., p. 521-526 6 p. 913361. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 2001-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cost functions

Integrated power supply planning and floorplanning

Liu, I. M., Chen, H. M., Chou, T. L., Aziz, A. & Wong, D. F., Jan 1 2001, Proceedings of the ASP-DAC 2001: Asia and South Pacific Design Automation Conference 2001. Institute of Electrical and Electronics Engineers Inc., p. 589-594 6 p. 913372. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 2001-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Planning
Networks (circuits)
Electric wiring
Power quality
Electric potential

LRoute: A delay minimal router for hierarchical CPLDs

Lee, K. K. & Wong, M. D. F., 2001, ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA. p. 12-20 9 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Routers
Field programmable gate arrays (FPGA)
Topology
Mathematical programming
Networks (circuits)

Memory-efficient interconnect optimization

Lai, M. & Wong, M. D. F., Jan 1 2001, Proceedings of the ASP-DAC 2001: Asia and South Pacific Design Automation Conference 2001. Institute of Electrical and Electronics Engineers Inc., p. 198-202 5 p. 913304. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 2001-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Dynamic programming
Data storage equipment
Networks (circuits)
Experiments
2000

Wire routing and satisfiability planning

Erdem, E., Lifschitz, V. & Wong, M. D. F., Jan 1 2000, Computational Logic - CL 2000 - 1st International Conference, Proceedings. Dahl, V., Furbach, U., Kerber, M., Palamidessi, C., Stuckey, P. J., Pereira, L. M., Sagiv, Y., Lloyd, J. & Lau, K-K. (eds.). Springer-Verlag, p. 822-836 15 p. (Lecture Notes in Artificial Intelligence (Subseries of Lecture Notes in Computer Science); vol. 1861).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Routing
Planning
Wire
Robot
Robots
1998

Exact tree-based FPGA technology mapping for logic blocks with independent LUTs

Korupolu, M. R., Lee, K. K. & Wong, M. D. F., Jan 1 1998, Proceedings 1998 - Design and Automation Conference, DAC 1998. Institute of Electrical and Electronics Engineers Inc., p. 708-711 4 p. 724563. (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Logic
Tree Networks
Exact Algorithms

Global routing with crosstalk constraints

Zhou, H. & Wong, M. D. F., Jan 1 1998, Proceedings 1998 - Design and Automation Conference, DAC 1998. Institute of Electrical and Electronics Engineers Inc., p. 374-377 4 p. 724500. (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Crosstalk
Routing
VLSI Layout
Steiner Tree
Lagrangian Relaxation

Integrated partitioning and scheduling for hardware/software co-design

Liu, H. & Wong, M. D. F., 1998, VLSI in Computers and Processors. IEEE, p. 609-614 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Scheduling
Hardware
Application specific integrated circuits
Computer hardware
Program processors
1997

Network flow based multi-way partitioning with area and pin constraints

Liu, H. & Wong, M. D. F., 1997, Proceedings of the International Symposium on Physical Design. ACM, p. 12-17 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Networks (circuits)

On the construction of universal series-parallel functions for logic module design

Young, F. Y. & Wong, M. D. F., 1997, Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Anon (ed.). IEEE, p. 482-488 7 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Boolean functions
Trees (mathematics)
Field programmable gate arrays (FPGA)
1995

Circuit clustering for delay minimization under area and pin constraints

Yang, H. & Wong, D. F., Mar 6 1995, Proceedings of the 1995 European Conference on Design and Test, EDTC 1995. Association for Computing Machinery, Inc, p. 65-70 6 p. (Proceedings of the 1995 European Conference on Design and Test, EDTC 1995).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Networks (circuits)
Delay circuits
Logic gates
Clustering algorithms
Field programmable gate arrays (FPGA)

On designing ULM-based FPGA logic modules

Thakur, S. & Wong, M. D. F., 1995, ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA. ACM, p. 3-9 7 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field programmable gate arrays (FPGA)
Networks (circuits)

Thermal placement for high-performance multichip modules

Chao, K. Y. & Wong, M. D. F., 1995, Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Anon (ed.). IEEE, p. 218-223 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Multichip modules
Cooling
Hot Temperature
Temperature
1993

Cell area minimization by transistor folding

Her, T. W. & Wong, D. F., Dec 1 1993, European Design Automation Conference - Proceedings. Anon (ed.). Publ by IEEE, p. 172-177 6 p. (European Design Automation Conference - Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Transistors

Fast Boolean matching for field-programmable gate arrays

Zhu, K. & Wong, D. F., Dec 1 1993, European Design Automation Conference - Proceedings. Anon (ed.). Publ by IEEE, p. 352-357 6 p. (European Design Automation Conference - Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field programmable gate arrays (FPGA)
Binary decision diagrams
Table lookup
Data storage equipment

Graph partitioning problem for multiple-chip design

Chen, Y. P., Wang, T. C. & Wong, D. F., Jan 1 1993, Proceedings - IEEE International Symposium on Circuits and Systems. Publ by IEEE, p. 1778-1781 4 p. (Proceedings - IEEE International Symposium on Circuits and Systems; vol. 3).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Networks (circuits)
Data flow graphs
Adders
Costs

HV/VH trees: a new spatial data structure for fast region queries

Lai, G. G., Fussell, D. & Wong, D. F., Jan 1 1993, Proceedings - Design Automation Conference. Publ by IEEE, p. 43-47 5 p. (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Data structures
Data storage equipment

On optimal approximation of orthogonal polygons

Chen, Y. P. & Wong, D. F., Jan 1 1993, Proceedings - IEEE International Symposium on Circuits and Systems. Publ by IEEE, p. 2533-2536 4 p. (Proceedings - IEEE International Symposium on Circuits and Systems; vol. 4).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Computational geometry
Image processing
Polynomials

On over the cell channel routing

Wang, T. C., Wong, M. D. F. & Wong, C. K., Dec 1 1993, European Design Automation Conference - Proceedings. Anon (ed.). Publ by IEEE, 1 p. (European Design Automation Conference - Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Optimal clustering for delay minimization

Rajaraman, R. & Wong, M. D. F., 1993, Proceedings - Design Automation Conference. Publ by IEEE, p. 309-314 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Combinatorial circuits
Polynomials
Networks (circuits)

Switch module design with application to two-dimensional segmentation design

Zhu, K., Wong, D. F. & Chang, Y. W., Dec 1 1993, Proc 1993 IEEE ACM Int Conf Comput Aided Des. Anon (ed.). Publ by IEEE, p. 480-485 6 p. (Proc 1993 IEEE ACM Int Conf Comput Aided Des).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Switches
Field programmable gate arrays (FPGA)
1992

Efficient shape curve construction in floorplan design

Wang, T. C. & Wong, M. D. F., 1992, Proc Eur Conf Des Autom. Publ by IEEE, p. 356-360 5 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Graph theoretic technique to speed up floorplan area optimization

Wang, T. C. & Wong, D. F., Dec 1 1992, Proceedings - Design Automation Conference. Publ by IEEE, p. 62-68 7 p. (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Data storage equipment
Polynomials

Minimizing channel density by shifting blocks and terminals

Cai, Y. & Wong, D. F., Dec 1 1992, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers. Publ by IEEE, p. 524-527 4 p. (1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Polynomials

On channel segmentation design for row-based FPGAs

Zhu, K. & Wong, D. F., Dec 1 1992, IEEE/ACM International Conference on Computer-Aided Design. Publ by IEEE, p. 26-29 4 p. (IEEE/ACM International Conference on Computer-Aided Design).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field programmable gate arrays (FPGA)

Optimal module implementation and its application to transistor placement

Her, T. W. & Wong, D. F., Dec 1 1992, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers. Publ by IEEE, p. 98-101 4 p. (1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Transistors
Satellites
Industry
1991

A general multi-layer area router

Guruswamy, M. & Wong, D. F., Jun 1 1991, Proceedings - Design Automation Conference. Publ by IEEE, p. 335-340 6 p. (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Routers
Electric wiring
Multilayers

Area of optimization for higher order hierarchical floorplans

The, K. S. & Wong, M. D. F., 1991, IEEE International Conference on Computer Design - VLSI in Computers and Processors. Publ by IEEE, p. 520-523 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Topology

Manifestation of faults to errors in signature analysis

Chan, J. C., Womack, B. F. & Wong, D. F., Dec 1 1991, IEEE International Conference on Computer Design - VLSI in Computers and Processors. Publ by IEEE, p. 360-363 4 p. (IEEE International Conference on Computer Design - VLSI in Computers and Processors).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Computer hardware
Testing

On minimizing the number of L-shaped channels

Cai, Y. & Wong, D. F., Jun 1 1991, Proceedings - Design Automation Conference. Publ by IEEE, p. 328-334 7 p. (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Routers
Decomposition
1990

A channel/switchbox definition algorithm for building-block layout

Cai, Y. & Wong, D. F., Dec 1 1990, 27th ACM/IEEE Design Automation Conference. Proceedings 1990. Publ by IEEE, p. 638-641 4 p. (27th ACM/IEEE Design Automation Conference. Proceedings 1990).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Electric switchgear
Polynomials
Decomposition

An optimal algorithm for floorplan area optimization

Wang, T. C. & Wong, D. F., Dec 1 1990, 27th ACM/IEEE Design Automation Conference. Proceedings 1990. Publ by IEEE, p. 180-186 7 p. (27th ACM/IEEE Design Automation Conference. Proceedings 1990).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Topology

An optimal channel pin assignment algorithm

Cai, Y. & Wong, D. F., Dec 1 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers. Publ by IEEE, p. 10-13 4 p. (1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Polynomials
Computational complexity

Optimal orientations of transistor chains

Her, T. W., Wong, D. F. & Freeman, T. H., Dec 1 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers. Publ by IEEE, p. 524-527 4 p. (1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Transistors
Satellites
Industry

Topological routing using geometric information

Haruyama, S., Wong, D. F. & Fussell, D., Dec 1 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers. Publ by IEEE, p. 6-9 4 p. (1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Wire
1989

Algorithm for hierarchical floorplan design

Wong, M. D. F. & The, K. S., 1989, IEEE Int Conf Comput Aided Des ICCAD 89 Dig Tech Pap. Anon (ed.). Publ by IEEE, p. 484-487 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Function evaluation
Simulated annealing
Cost functions
Automation
1988

Channel routing order for building-block layout with rectilinear modules

Guruswamy, M. & Wong, D. F., Dec 1 1988, IEEE Int Conf on Comput Aided Des ICCAD 88 a Conf for the EE CAD Prof. Publ by IEEE, p. 184-187 4 p. (IEEE Int Conf on Comput Aided Des ICCAD 88 a Conf for the EE CAD Prof).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

How to obtain more compactable channel routing solutions.

Cong, J. & Wong, D. F., Dec 1 1988, Proceedings - Design Automation Conference. Publ by IEEE, p. 663-666 4 p. (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Compaction
Routers

Topological channel routing

Haruyama, S., Wong, M. D. F. & Fussell, D., 1988, IEEE Int Conf on Comput Aided Des ICCAD 88 a Conf for the EE CAD Prof. Publ by IEEE, p. 406-409 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Wire
1987

ARRAY OPTIMIZATION FOR VLSI SYNTHESIS.

Wong, M. D. F. & Liu, C. L., Jan 1 1987, Proceedings - Design Automation Conference. IEEE, p. 537-543 7 p. (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Simulated annealing

ENHANCED BOTTOM-UP ALGORITHM FOR FLOORPLAN DESIGN.

Mueller, T. R., Wong, D. F. & Liu, C. L., Dec 1 1987, Unknown Host Publication Title. IEEE, p. 524-527 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Simulated annealing

FLOORPLAN DESIGN FOR RECTANGULAR AND L-SHAPED MODULES.

Wong, D. F. & Liu, C. L., Dec 1 1987, Unknown Host Publication Title. IEEE, p. 520-523 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Pascal (programming language)
Simulated annealing

NEW APPROACH TO THE THREE LAYER CHANNEL ROUTING PROBLEM.

Cong, J., Wong, D. F. & Liu, C. L., Dec 1 1987, Unknown Host Publication Title. IEEE, p. 378-381 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Routers
1985

SIMULATED-ANNEALING CHANNEL ROUTER.

Leong, H. W., Wong, D. F. & Liu, C. L., Dec 1 1985, Unknown Host Publication Title. IEEE, p. 226-228 3 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Simulated annealing
Routers