Computer Science
Assignment Problem
10%
Benchmark Circuit
8%
Buffer Insertion
20%
Building-Blocks
13%
Channel Density
6%
Coupling Capacitance
9%
Data Structure
6%
Delay Minimization
10%
Dynamic Power
9%
Efficient Algorithm
7%
Elmore Delay Model
8%
Exact Algorithm
14%
Experimental Result
100%
Fast Algorithm
11%
Field Programmable Gate Arrays
71%
Floorplan Area
9%
Floorplan Design
12%
Floorplanning
26%
Global Routing
17%
Graphics Processing Unit
29%
Integrated Circuit
12%
Lagrangian Relaxation
18%
Learning System
10%
Machine Learning
10%
Mapping Algorithm
6%
Microarchitecture
8%
Open Source
9%
Optimal Algorithm
37%
Optimization Problem
7%
Performance Requirement
6%
Physical Design
7%
Pin Assignment
10%
Placement Algorithm
6%
Polynomial Time
25%
Polynomial Time Algorithm
7%
Process Variation
8%
Routing Algorithm
32%
Routing Channel
13%
Routing Problem
47%
Routing Resource
10%
Routing Solution
25%
Shortest Path Problem
11%
Simulated Annealing
11%
Slicing Floorplan
11%
Solution Quality
9%
Speed-up
17%
Technology Mapping
12%
Timing Analysis
22%
Timing Constraint
6%
Total Wirelength
6%
Keyphrases
Buffer Insertion
21%
Channel Routing
20%
Circuit Partitioning
13%
Coupling Capacitance
9%
Deep Submicron
11%
Delay Minimization
10%
Directed Self-assembly
11%
Double Patterning Lithography
9%
Elmore Delay Model
12%
Escape Routing
22%
Exact Algorithm
14%
Fast Algorithm
9%
Field Programmable Gate Arrays
11%
Floor Plan Design
12%
Floorplanning
42%
Flow-based
10%
Global Routing
15%
GPU Acceleration
10%
High Performance
15%
Lagrangian Relaxation
14%
Layer Assignment
10%
Lithography
11%
Logic Module
9%
Low Power
9%
Mask Optimization
9%
Maze Routing
13%
Network Flow
13%
Optical Proximity Correction
12%
Optimal Algorithm
22%
Pin Assignment
13%
Polynomial Time
23%
Power Grid
10%
Routability
14%
Router
26%
Routing Algorithm
25%
Routing Problem
24%
Routing Solution
18%
Self-aligned Double Patterning
11%
Simulated Annealing
10%
Slicing Floorplan
10%
Switch Module
9%
Technology Mapping
11%
Time Constraints
11%
Timing Analysis
17%
Timing-driven
9%
Triple Patterning Lithography
9%
Voltage Islands
10%
Wire Segments
9%
Wire Sizing
27%
Wirelength
16%
Engineering
Building Block
7%
Channel Layer
6%
Circuit Performance
6%
Constraint Length
5%
Coupling Capacitance
8%
Critical Cell
6%
Crosstalk
11%
Design Flow
6%
Design Power
5%
Design Rule
9%
Electric Power Utilization
6%
Exact Algorithm
12%
Experimental Result
45%
Extreme-Ultraviolet Lithography
7%
Fast Algorithm
7%
Field Programmable Gate Arrays
20%
Graphics Processing Unit
8%
Integrated Circuit
5%
Interconnects
13%
Lagrangian Relaxation
8%
Linear Programming
9%
Linear Time
8%
Lithography
42%
Manufacturability
10%
Metal Layer
5%
Nodes
23%
Pin Assignment
9%
Polynomial Time
21%
Power Grid
7%
Routing Algorithm
10%
Routing Problem
19%
Routing Solution
12%
Supply Voltage
5%
