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Computer Science
Assignment Problem
9%
Benchmark Circuit
7%
Buffer Insertion
19%
Building-Blocks
12%
Coupling Capacitance
9%
Data Structure
6%
Delay Minimization
9%
Dynamic Power
8%
Efficient Algorithm
7%
Elmore Delay Model
8%
Exact Algorithm
13%
Experimental Result
100%
Fast Algorithm
11%
Field Programmable Gate Arrays
68%
Floorplan Area
8%
Floorplan Design
11%
Floorplanning
25%
Global Placement
6%
Global Routing
16%
Graphics Processing Unit
29%
Integrated Circuit
13%
Lagrangian Relaxation
18%
Learning System
10%
Machine Learning
10%
Mapping Algorithm
6%
Microarchitecture
7%
Neural Network
6%
Open Source
8%
Optimal Algorithm
35%
Optimization Problem
7%
Performance Requirement
6%
Physical Design
6%
Pin Assignment
10%
Placement Algorithm
6%
Polynomial Time
24%
Polynomial Time Algorithm
7%
Process Variation
8%
Routing Algorithm
30%
Routing Channel
12%
Routing Problem
44%
Routing Resource
9%
Routing Solution
24%
Shortest Path Problem
11%
Simulated Annealing
11%
Slicing Floorplan
11%
Solution Quality
8%
Speed-up
16%
Technology Mapping
11%
Timing Analysis
21%
Total Wirelength
6%
Keyphrases
Buffer Insertion
19%
Channel Routing
19%
Circuit Partitioning
13%
Coupling Capacitance
8%
Deep Submicron
10%
Delay Minimization
10%
Directed Self-assembly
11%
Double Patterning Lithography
8%
Elmore Delay Model
11%
Escape Routing
21%
Exact Algorithm
13%
Fast Algorithm
8%
Field Programmable Gate Arrays
11%
Floor Plan Design
12%
Floorplanning
40%
Flow-based
9%
Global Routing
14%
GPU Acceleration
10%
High Performance
15%
Lagrangian Relaxation
13%
Layer Assignment
10%
Lithography
11%
Logic Module
9%
Low Power
9%
Mask Optimization
9%
Maze Routing
13%
Network Flow
12%
Optical Proximity Correction
12%
Optimal Algorithm
21%
Pin Assignment
12%
Polynomial Time
22%
Power Grid
9%
Routability
13%
Router
25%
Routing Algorithm
24%
Routing Problem
23%
Routing Solution
17%
Self-aligned Double Patterning
10%
Simulated Annealing
9%
Slicing Floorplan
9%
Switch Module
9%
Technology Mapping
11%
Time Constraints
10%
Time-optimal Algorithm
8%
Timing Analysis
16%
Timing-driven
10%
Triple Patterning Lithography
9%
Wire Segments
9%
Wire Sizing
26%
Wirelength
16%
Engineering
Building Block
6%
Channel Layer
5%
Circuit Performance
5%
Constraint Length
5%
Coupling Capacitance
8%
Crosstalk
11%
Design Flow
6%
Design Rule
9%
Electric Power Utilization
6%
Exact Algorithm
11%
Experimental Result
46%
Extreme-Ultraviolet Lithography
6%
Fast Algorithm
7%
Field Programmable Gate Arrays
19%
Graphics Processing Unit
7%
Integrated Circuit
5%
Interconnects
13%
Lagrangian Relaxation
7%
Linear Programming
8%
Linear Time
8%
Lithography
43%
Manufacturability
10%
Nodes
22%
Pin Assignment
9%
Polynomial Time
20%
Power Grid
6%
Routing Algorithm
9%
Routing Problem
18%
Routing Solution
12%
Supply Voltage
5%
