Computer Science
Experimental Result
100%
Routing Problem
44%
Optimal Algorithm
36%
Routing Algorithm
31%
Floorplanning
26%
Polynomial Time
25%
Routing Solution
25%
Timing Analysis
20%
Buffer Insertion
19%
Lagrangian Relaxation
18%
Speed-up
17%
Global Routing
15%
Integrated Circuits
14%
Exact Algorithm
13%
Routing Channel
13%
Routing Resource
13%
Building-Blocks
12%
Technology Mapping
12%
Fast Algorithm
12%
Field Programmable Gate Arrays
11%
Floorplan Design
11%
Simulated Annealing
11%
Slicing Floorplan
11%
Shortest Path Problem
11%
Benchmark Circuit
10%
Pin Assignment
10%
Machine Learning
10%
Delay Minimization
9%
Assignment Problem
9%
Coupling Capacitance
9%
Dynamic Power
9%
Floorplan Area
8%
Solution Quality
8%
Process Variation
8%
Elmore Delay Model
8%
Timing Constraint
8%
Microarchitecture
7%
Physical Design
7%
Efficient Algorithm
7%
Polynomial Time Algorithm
7%
Open Source
7%
Optimization Problem
7%
Approximation Algorithms
6%
Mapping Algorithm
6%
Placement Algorithm
6%
Data Structure
6%
Neural Network
6%
Channel Density
6%
Performance Requirement
6%
Total Wirelength
6%
Keyphrases
Floorplanning
40%
Wire Sizing
26%
Router
25%
Routing Algorithm
23%
Routing Problem
22%
Polynomial Time
22%
Optimal Algorithm
21%
Escape Routing
21%
Buffer Insertion
20%
Channel Routing
19%
Routing Solution
17%
Timing Analysis
16%
Wirelength
15%
High Performance
15%
Exact Algorithm
13%
Lagrangian Relaxation
13%
Circuit Partitioning
13%
Global Routing
13%
Maze Routing
12%
Routability
12%
Pin Assignment
12%
Network Flow
12%
Floor Plan Design
12%
Elmore Delay Model
11%
Lithography
11%
Field Programmable Gate Arrays
11%
Directed Self-assembly
11%
Technology Mapping
11%
Time Constraints
10%
Self-aligned Double Patterning
10%
Deep Submicron
10%
Layer Assignment
10%
Delay Minimization
10%
Power Grid
9%
Slicing Floorplan
9%
Flow-based
9%
Optical Proximity Correction
9%
Simulated Annealing
9%
Voltage Islands
9%
Low Power
9%
Wire Segments
9%
Logic Module
9%
Triple Patterning Lithography
9%
Switch Module
9%
Mask Optimization
9%
Timing-driven
8%
Coupling Capacitance
8%
GPU Acceleration
8%
Fast Algorithm
8%
Double Patterning Lithography
8%
Engineering
Lithography
40%
Experimental Result
38%
Nodes
21%
Polynomial Time
20%
Routing Problem
18%
Field Programmable Gate Arrays
17%
Interconnects
13%
Routing Solution
12%
Exact Algorithm
11%
Crosstalk
11%
Manufacturability
10%
Routing Algorithm
9%
Pin Assignment
9%
Design Rule
8%
Linear Programming
8%
Coupling Capacitance
8%
Linear Time
8%
Defects
7%
Lagrangian Relaxation
7%
Graphics Processing Unit
7%
Power Grid
6%
Building Block
6%
Design Flow
6%
Electric Power Utilization
6%
Fast Algorithm
6%
Circuit Performance
5%
Critical Cell
5%
Channel Layer
5%
Supply Voltage
5%
Constraint Length
5%
Integrated Circuit
5%
