Computer Science
Experimental Result
100%
Field Programmable Gate Arrays
71%
Routing Problem
47%
Optimal Algorithm
37%
Routing Algorithm
32%
Graphics Processing Unit
29%
Floorplanning
26%
Routing Solution
25%
Polynomial Time
25%
Timing Analysis
22%
Buffer Insertion
20%
Lagrangian Relaxation
18%
Global Routing
17%
Speed-up
17%
Exact Algorithm
14%
Building-Blocks
13%
Routing Channel
13%
Integrated Circuit
12%
Technology Mapping
12%
Floorplan Design
12%
Simulated Annealing
11%
Slicing Floorplan
11%
Shortest Path Problem
11%
Fast Algorithm
11%
Pin Assignment
10%
Learning System
10%
Machine Learning
10%
Routing Resource
10%
Delay Minimization
10%
Assignment Problem
10%
Coupling Capacitance
9%
Open Source
9%
Solution Quality
9%
Floorplan Area
9%
Dynamic Power
9%
Process Variation
8%
Elmore Delay Model
8%
Microarchitecture
8%
Benchmark Circuit
8%
Polynomial Time Algorithm
7%
Optimization Problem
7%
Efficient Algorithm
7%
Physical Design
7%
Mapping Algorithm
6%
Data Structure
6%
Placement Algorithm
6%
Performance Requirement
6%
Total Wirelength
6%
Timing Constraint
6%
Channel Density
6%
Keyphrases
Floorplanning
42%
Wire Sizing
27%
Router
26%
Routing Algorithm
25%
Routing Problem
24%
Polynomial Time
23%
Optimal Algorithm
22%
Escape Routing
22%
Buffer Insertion
21%
Channel Routing
20%
Routing Solution
18%
Timing Analysis
17%
Wirelength
16%
High Performance
15%
Global Routing
15%
Routability
14%
Exact Algorithm
14%
Lagrangian Relaxation
14%
Maze Routing
13%
Circuit Partitioning
13%
Pin Assignment
13%
Network Flow
13%
Floor Plan Design
12%
Optical Proximity Correction
12%
Elmore Delay Model
12%
Field Programmable Gate Arrays
11%
Directed Self-assembly
11%
Technology Mapping
11%
Lithography
11%
Time Constraints
11%
Self-aligned Double Patterning
11%
Deep Submicron
11%
GPU Acceleration
10%
Layer Assignment
10%
Delay Minimization
10%
Power Grid
10%
Slicing Floorplan
10%
Flow-based
10%
Simulated Annealing
10%
Voltage Islands
10%
Low Power
9%
Wire Segments
9%
Logic Module
9%
Triple Patterning Lithography
9%
Mask Optimization
9%
Switch Module
9%
Timing-driven
9%
Coupling Capacitance
9%
Fast Algorithm
9%
Double Patterning Lithography
9%
Engineering
Experimental Result
45%
Lithography
42%
Nodes
23%
Polynomial Time
21%
Field Programmable Gate Arrays
20%
Routing Problem
19%
Interconnects
13%
Routing Solution
12%
Exact Algorithm
12%
Crosstalk
11%
Manufacturability
10%
Routing Algorithm
10%
Design Rule
9%
Pin Assignment
9%
Linear Programming
9%
Coupling Capacitance
8%
Linear Time
8%
Lagrangian Relaxation
8%
Graphics Processing Unit
8%
Fast Algorithm
7%
Power Grid
7%
Building Block
7%
Extreme-Ultraviolet Lithography
7%
Design Flow
6%
Electric Power Utilization
6%
Circuit Performance
6%
Critical Cell
6%
Channel Layer
6%
Supply Voltage
5%
Integrated Circuit
5%
Constraint Length
5%
Metal Layer
5%
Design Power
5%
