Josep Torrellas

1990 …2019
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Research Output 1990 2019

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Article
2018

Medium Access Control in Wireless Network-on-Chip: A Context Analysis

Abadal, S., Mestres, A., Torrellas, J., Alarcon, E. & Cabellos-Aparicio, A., Jun 2018, In : IEEE Communications Magazine. 56, 6, p. 172-178 7 p.

Research output: Contribution to journalArticle

Medium access control
Wireless networks
Communication
Throughput
Network protocols

OrthoNoC: A Broadcast-Oriented Dual-Plane Wireless Network-on-Chip Architecture

Abadal, S., Torrellas, J., Alarcon, E. & Cabellos-Aparicio, A., Mar 1 2018, In : IEEE Transactions on Parallel and Distributed Systems. 29, 3, p. 628-641 14 p., 8078211.

Research output: Contribution to journalArticle

Wireless networks
Communication
Interfaces (computer)
Scalability
Energy conservation
2016

Extreme-scale computer architecture

Torrellas, J., Mar 26 2016, In : National Science Review. 3, 1, p. 19-23 5 p.

Research output: Contribution to journalArticle

2015

Asymmetric memory fences: Optimizing both performance and implementability

Duan, Y., Honarmand, N. & Torrellas, J., Apr 2015, In : ACM SIGPLAN Notices. 50, 4, p. 531-543 13 p.

Research output: Contribution to journalArticle

Fences
Data storage equipment
Taxonomies
2014

Improving JavaScript performance by deconstructing the type system

Ahn, W., Choi, J., Shull, T., Garzaran, M. J. & Torrellas, J., Jun 5 2014, In : ACM SIGPLAN Notices. 49, 6, p. 496-507 12 p.

Research output: Contribution to journalArticle

Websites
Code generation
2013

Coping with parametric variation at near-threshold voltages

Karpuzcu, U. R., Kim, N. S. & Torrellas, J., Sep 9 2013, In : IEEE Micro. 33, 4, p. 6-14 9 p., 6527886.

Research output: Contribution to journalArticle

Threshold voltage
Energy efficiency

Cyrus: Unintrusive application-level record-replay for replay parallelism

Honarmand, N., Dautenhahn, N., Torrellas, J., King, S. T., Pokam, G. & Pereira, C., Apr 1 2013, In : ACM SIGPLAN Notices. 48, 4, p. 193-206 14 p.

Research output: Contribution to journalArticle

Hardware
Program debugging
Fault tolerance

DeAliaser: Alias speculation using atomic region support

Ahn, W., Duan, Y. & Torrellas, J., Apr 1 2013, In : ACM SIGPLAN Notices. 48, 4, p. 167-180 14 p.

Research output: Contribution to journalArticle

Computer hardware
Redundancy
Hardware
Data storage equipment
Recovery

Volition: Scalable and precise sequential consistency violation detection

Qian, X., Torrellas, J., Sahelices, B. & Qian, D., Apr 1 2013, In : ACM SIGPLAN Notices. 48, 4, p. 535-548 14 p.

Research output: Contribution to journalArticle

Data storage equipment
Hardware
2009

Architectures for extreme-scale computing

Torrellas, J., Nov 1 2009, Computer, 42, 11, p. 28-35 8 p.

Research output: Contribution to specialist publicationArticle

Threshold voltage
Phase change memory
Photonics
Transistors
Electric power utilization

Capo: A software-hardware interface for practical deterministic multiprocessor replay ?

Montesinos, P., Hicks, M., King, S. T. & Torrellas, J., Mar 1 2009, In : ACM SIGPLAN Notices. 44, 3, p. 73-84 12 p.

Research output: Contribution to journalArticle

Hardware

SoftSig: Software-exposed hardware signatures for code analysis and optimization

Tuck, J., Ahn, W., Torrellas, J. & Ceze, L., Apr 1 2009, In : IEEE Micro. 29, 1, p. 84-95 12 p.

Research output: Contribution to journalArticle

Hardware

The Bulk Multicore architecture for improved programmability

Torrellas, J., Ceze, L., Tuck, J., Cascaval, C., Montesinos, P., Ahn, W. & Prvulovic, M., Dec 1 2009, In : Communications of the ACM. 52, 12, p. 58-65 8 p.

Research output: Contribution to journalArticle

Hardware
Parallel programming
Computer hardware
Data storage equipment

Two hardware-based approaches for deterministic multiprocessor replay

Hower, D. R., Montesinos, P., Ceze, L., Hill, M. D. & Torrellas, J., Jun 1 2009, In : Communications of the ACM. 52, 6, p. 93-100 8 p.

Research output: Contribution to journalArticle

Computer hardware
Computer systems
Data storage equipment
Travel time
Dynamic mechanical analysis
2008

SoftSig: Software-exposed hardware signatures for code analysis and optimization

Tuck, J., Ahn, W., Ceze, L. & Torrellas, J., Mar 1 2008, In : ACM SIGPLAN Notices. 43, 3, p. 145-156 12 p.

Research output: Contribution to journalArticle

Hardware

VARIUS: A model of process variation and resulting timing errors for microarchitects

Sarangi, S. R., Greskamp, B., Teodorescu, R., Nakano, J., Tiwari, A. & Torrellas, J., Feb 1 2008, In : IEEE Transactions on Semiconductor Manufacturing. 21, 1, p. 3-13 11 p.

Research output: Contribution to journalArticle

time measurement
microprocessors
clocks
central processing units
Microprocessor chips
2007

Patching processor design errors with programmable hardware

Sarangi, S., Narayanasamy, S., Carneal, B., Tiwari, A., Calder, B. & Torrellas, J., Jan 1 2007, In : IEEE Micro. 27, 1, p. 12-25 14 p.

Research output: Contribution to journalArticle

Hardware
Watches

Threshold voltage variation effects on aging-related hard failure rates

Greskamp, B., Sarangi, S. R. & Torrellas, J., 2007, In : Proceedings - IEEE International Symposium on Circuits and Systems. p. 1261-1264 4 p., 4252875.

Research output: Contribution to journalArticle

Threshold voltage
Aging of materials
Heat resistance
2006

CAVA: Using Checkpoint-Assisted Value Prediction to Hide L2 Misses

Ceze, L., Strauss, K., Tuck, J., Torrellas, J. & Renau, J., Jan 1 2006, In : ACM Transactions on Architecture and Code Optimization. 3, 2, p. 182-208 27 p.

Research output: Contribution to journalArticle

Data storage equipment

Energy-efficient thread-level speculation

Renau, J., Strauss, K., Ceze, L., Liu, W., Sarangi, S. R., Tuck, J. & Torrellas, J., Jan 1 2006, In : IEEE Micro. 26, 1, p. 80-91 12 p.

Research output: Contribution to journalArticle

Swich: A prototype for efficient cache-level checkpointing and rollback

Teodorescu, R., Nakano, J. & Torrellas, J., Sep 1 2006, In : IEEE Micro. 26, 5, p. 28-40 13 p.

Research output: Contribution to journalArticle

Field programmable gate arrays (FPGA)
2005

Efficient and Flexible Architectural Support for Dynamic Monitoring

Zhou, Y., Zhou, P., Qin, F., Liu, W. & Torrellas, J., Jan 1 2005, In : ACM Transactions on Architecture and Code Optimization. 2, 1, p. 3-33 31 p.

Research output: Contribution to journalArticle

Monitoring
Data storage equipment
Computer architecture
Dynamic loads
Detectors

Tradeoffs in Buffering Speculative Memory State for Thread-Level Speculation in Multiprocessors

Garzaran, M. J., Torrellas, J., Prvulovic, M., Llaberia, J. M., Douillet, V. V. & Rauchwerger, L., Jan 1 2005, In : ACM Transactions on Architecture and Code Optimization. 2, 3, p. 247-279 33 p.

Research output: Contribution to journalArticle

Data storage equipment
Taxonomies
Merging
2004

CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction

Ceze, L., Strauss, K., Tuck, J. & Torrellas, J., Jan 2004, In : IEEE Computer Architecture Letters. 3, 1, 1 p.

Research output: Contribution to journalArticle

Data storage equipment

Iwatcher: Simple general architectural support for software debugging

Zhou, P., Qin, F., Liu, W., Zhou, Y. & Torrellas, J., Nov 1 2004, In : IEEE Micro. 24, 6, p. 50-56 7 p.

Research output: Contribution to journalArticle

Hardware
Data storage equipment
Monitoring
2003

Correlation prefetching with a user-level memory thread

Solihin, Y., Lee, J. & Torrellas, J., Jun 1 2003, In : IEEE Transactions on Parallel and Distributed Systems. 14, 6, p. 563-580 18 p.

Research output: Contribution to journalArticle

Data storage equipment
Dynamic random access storage
Computer hardware
Data structures
Controllers
Subroutines
Testing
Energy conservation
Servers
Experiments

Programming the FlexRAM parallel intelligent memory system

Fraguela, B. B., Renau, J., Featrier, P., Padua, D. A. & Torrellas, J., Oct 2003, In : ACM SIGPLAN Notices. 38, 10, p. 49-60 12 p.

Research output: Contribution to journalArticle

Computer programming
Computer systems
Data storage equipment
Memory architecture
Servers
2002
Hardware
Data storage equipment
Recovery
Availability
Costs

Software Trace Cache for Commercial Applications

Ramirez, A., Larriba-Pey, J. L., Navarro, C., Valero, M. & Torrellas, J., Oct 1 2002, In : International Journal of Parallel Programming. 30, 5, p. 373-395 23 p.

Research output: Contribution to journalArticle

Cache
Trace
Hardware
Software
Superscalar Processor

Speculative synchronization: Applying thread-level speculation to explicitly parallel applications

Martínez, J. F. & Torrellas, J., Dec 1 2002, In : Operating Systems Review (ACM). 36, 5, p. 18-29 12 p.

Research output: Contribution to journalArticle

Synchronization
Hardware

Using a user-level memory thread for correlation prefetching

Solihin, Y., Lee, J. & Torrellas, J., Jan 1 2002, In : Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA. p. 171-182 12 p.

Research output: Contribution to journalArticle

Data storage equipment
Dynamic random access storage
Computer hardware
Data structures
Controllers
2001
Shared-memory multiprocessors
Parallelization
Data storage equipment
Speedup
Architecture

Automatic code mapping on an intelligent memory architecture

Solihin, Y., Lee, J. & Torrellas, J., Nov 2001, In : IEEE Transactions on Computers. 50, 11, p. 1248-1266 19 p.

Research output: Contribution to journalArticle

Memory architecture
Data storage equipment
Multiprocessor Systems
Overlap
High Performance
Scalability
Architectural design
Data storage equipment

The design of DEETM: A framework for dynamic energy efficiency and temperature management

Huang, M., Renau, J., Yoo, S. M. & Torrellas, J., Dec 1 2001, In : Journal of Instruction-Level Parallelism. 3

Research output: Contribution to journalArticle

Energy management
Energy efficiency
Temperature control
Temperature
Energy conservation

The Need for Fast Communication in Hardware-Based Speculative Chip Multiprocessors

Krishnan, V. & Torrellas, J., Dec 1 2001, In : International Journal of Parallel Programming. 29, 1, p. 3-33 31 p.

Research output: Contribution to journalArticle

Chip multiprocessors
Hardware
Thread
Communication
High Performance
1999

A chip-multiprocessor architecture with speculative multithreading

Krishnan, V. & Torrellas, J., Dec 1 1999, In : IEEE Transactions on Computers. 48, 9, p. 866-880 15 p.

Research output: Contribution to journalArticle

Chip multiprocessors
Multithreading
Computer hardware
Speculative Execution
Hardware

Cache-only memory architectures

Dahlgren, F. & Torrellas, J., Jun 1 1999, Computer, 32, 6, p. 72-79 8 p.

Research output: Contribution to specialist publicationArticle

Memory architecture
Data storage equipment
Hardware
Data storage equipment
Costs
Hardware

Comprehensive hardware and software support for operating systems to exploit MP memory hierarchies

Xia, C. & Torrellas, J., Jan 1 1999, In : IEEE Transactions on Computers. 48, 5, p. 494-505 12 p.

Research output: Contribution to journalArticle

Memory Hierarchy
Computer operating systems
Operating Systems
Computer hardware
Prefetching

Excel-NUMA: Toward programmability, simplicity, and high performance

Zhang, Z., Cintra, M. & Torrellas, J., Dec 1 1999, In : IEEE Transactions on Computers. 48, 2, p. 256-264 9 p.

Research output: Contribution to journalArticle

Excel
Simplicity
High Performance
Data storage equipment
Hardware
Chip multiprocessors
Hardware
Thread
Communication
High Performance
1998

Optimizing the instruction cache performance of the operating system

Torrellas, J., Xia, C. & Daigle, R. L., Dec 1 1998, In : IEEE Transactions on Computers. 47, 12, p. 1363-1381 19 p.

Research output: Contribution to journalArticle

Operating Systems
Cache
Locality
Hits
Percent
1997

The performance of the cedar multistage switching network

Torrellas, J. & Zhang, Z., Dec 1 1997, In : IEEE Transactions on Parallel and Distributed Systems. 8, 4, p. 321-336 16 p.

Research output: Contribution to journalArticle

Switching networks
Data storage equipment
Telecommunication traffic
Analytical models
Hardware
1996
Message passing
Flow control
Computer hardware
Data storage equipment
Hardware
Data storage equipment
Costs
1995

Evaluating the performance of cache-affinity scheduling in shared-memory multiprocessors

Torrellas, J., Tucker, A. & Gupta, A., Feb 1 1995, In : Journal of Parallel and Distributed Computing. 24, 2, p. 139-151 13 p.

Research output: Contribution to journalArticle

Shared-memory multiprocessors
Cache
Affine transformation
Workload
Scheduling
1994

Efficient algorithm for the run-time parallelization of DOACROSS loops

Chen, D. K., Torrellas, J. & Yew, P. C., 1994, In : Proceedings of the ACM/IEEE Supercomputing Conference. p. 518-527 10 p.

Research output: Contribution to journalArticle

Data storage equipment
Communication

False Sharing and Spatial Locality in Multiprocessor Caches

Torrellas, J., Lam, M. S. & Hennessy, J. L., Jun 1994, In : IEEE Transactions on Computers. 43, 6, p. 651-663 13 p.

Research output: Contribution to journalArticle

Multiprocessor
Locality
Cache
Sharing
Data storage equipment