Josep Torrellas

1990 …2019
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Research Output 1990 2019

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Augmint multiprocessor simulation toolkit for Intel x86 architectures

Nguyen, A. T., Michael, M., Sharma, A. & Torrellas, J., Dec 1 1996, p. 486-490. 5 p.

Research output: Contribution to conferencePaper

Simulators
Reduced instruction set computing
UNIX
Macros
Data storage equipment

Automatically mapping code on an intelligent memory architecture

Lee, J., Solihin, Y. & Torrellas, J., Jan 1 2001, p. 121-132. 12 p.

Research output: Contribution to conferencePaper

Memory architecture
Data storage equipment
Costs

Detailed characterization of a Quad Pentium Pro server running TPC-D

Cao, Q., Trancoso, P., Larriba-Pey, J. L., Torrellas, J., Knighten, R. & Won, Y., Dec 1 1999, p. 108-115. 8 p.

Research output: Contribution to conferencePaper

Servers
Computer hardware
Tuning
Costs

Energy-efficient hybrid wakeup logic

Huang, M., Renau, J. & Torrellas, J., Dec 1 2002, p. 196-201. 6 p.

Research output: Contribution to conferencePaper

Energy conservation
Energy utilization

Enhancing memory use in simple Coma: Multiplexed simple Coma

Basu, S. & Torrellas, J., Jan 1 1998, p. 152-161. 10 p.

Research output: Contribution to conferencePaper

Memory architecture
Data storage equipment
Computer hardware
Costs

FlexRAM: Toward an advanced Intelligent Memory system

Kang, Y., Huang, W., Yoo, S. M., Keen, D., Ge, Z., Lam, V., Pattnaik, P. & Torrellas, J., Dec 1 1999, p. 192-201. 10 p.

Research output: Contribution to conferencePaper

Data storage equipment
Dynamic random access storage
Computer systems
General purpose computers
Computer programming

Hardware for speculative parallelization of partially-parallel loops in DSM multiprocessors

Zhang, Y., Rauchwerger, L. & Torrellas, J., Jan 1 1999, p. 135-139. 5 p.

Research output: Contribution to conferencePaper

Scheduling
Hardware

Illinois aggressive coma multiprocessor project (I-ACOMA)

Torrellas, J. & Padua, D. A., Dec 1 1996, p. 106-111. 6 p.

Research output: Contribution to conferencePaper

Data storage equipment
Parallel programming
Parallel processing systems
Computer hardware

Improving the performance of bristled CC-NUMA systems using virtual channels and adaptivity

Martinez, J. F., Torrellas, J. & Duato, J., Jan 1 1999, p. 202-209. 8 p.

Research output: Contribution to conferencePaper

Routers
Bandwidth
Processing
Telecommunication networks
Scalability

L1 data cache decomposition for energy efficiency

Huang, M., Renau, J., Yoo, S. M. & Torrellas, J., Jan 1 2001, p. 10-15. 6 p.

Research output: Contribution to conferencePaper

Energy efficiency
Decomposition

Programming the FlexRAM parallel intelligent memory system

Fraguela, B. B., Renau, J., Feautrier, P., Padua, D. A. & Torrellas, J., Jul 28 2003, p. 49-60. 12 p.

Research output: Contribution to conferencePaper

Computer programming
Computer systems
Data storage equipment
Memory architecture
Servers

Software Trace Cache

Ramirez, A., Larriba-Pey, J. L., Navarro, C., Torrellas, J. & Valero, M., Jan 1 1999, p. 119-126. 8 p.

Research output: Contribution to conferencePaper

Hardware
Bandwidth

Speculative synchronization: Applying thread-level speculation to explicitly parallel applications

Martínez, J. F. & Torrellas, J., Dec 1 2002, p. 18-29. 12 p.

Research output: Contribution to conferencePaper

Synchronization
Hardware

Speeding up irregular applications in shared-memory multiprocessors: memory binding and group prefetching

Zhang, Z. & Torrellas, J., Jan 1 1995, p. 188-199. 12 p.

Research output: Contribution to conferencePaper

Data storage equipment
Computer aided design
Hardware

Speeding up the memory hierarchy in flat COMA multiprocessors

Yang, L. & Torrellas, J., Jan 1 1997, p. 4-13. 10 p.

Research output: Contribution to conferencePaper

Data storage equipment
Memory architecture
Dynamic random access storage
Computer operating systems
Hardware

Tasking with out-of-order spawn in TLS chip multiprocessors: Microarchitecture and compilation

Renau, J., Tuck, J., Liu, W., Ceze, L., Strauss, K. & Torrellas, J., Dec 1 2005, p. 179-188. 10 p.

Research output: Contribution to conferencePaper

Subroutines
Resource allocation
Hardware

Thread-level speculation on a CMP can be energy efficient

Renau, J., Strauss, K., Ceze, L., Liu, W., Sarangi, S., Tuck, J. & Torrellas, J., Dec 1 2005, p. 219-228. 10 p.

Research output: Contribution to conferencePaper

Energy utilization
Energy conservation
Costs

Toward a cost-effective DSM organization that exploits processor-memory integration

Torrellas, J., Yang, L. & Nguyen, A. T., Dec 1 2000, p. 15-25. 11 p.

Research output: Contribution to conferencePaper

Data storage equipment
Costs
Microprocessor chips
Hardware
Transistors

Toward a cost-effective DSM organization that exploits processor-memory integration

Torrellas, J., Yang, L. & Nguyen, A. T., Dec 1 1999, p. 15-25. 11 p.

Research output: Contribution to conferencePaper

Data storage equipment
Costs
Microprocessor chips
Hardware
Transistors

Use IRAM for rasterization

Kang, Y., Torrellas, J. & Huang, T. S., Dec 1 1998, p. 1010-1013. 4 p.

Research output: Contribution to conferencePaper

Dynamic random access storage
Random access storage
Parallel processing systems
Data storage equipment
Rasterization