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Keyphrases
ESD Protection
100%
Electrostatic Discharge
77%
Circuit Simulation
54%
Protection Device
54%
System-level ESD
51%
On chip
47%
Latch-up
46%
ESD Protection Device
46%
Charged Device Model
45%
Compact Model
44%
Thermoelectric Properties
34%
Electrostatic Discharge (ESD) Protection
31%
MOSFET
31%
Transistor
31%
Circuit-level Simulation
29%
NMOSFET
26%
Diode
26%
Circuit Level
26%
Wafer Level
25%
Silicon-controlled Rectifier
24%
Chip-level
24%
Protection Level
23%
CMOS Technology
23%
Protection Circuit
21%
CMOS VLSI
20%
Soft Failure
20%
Gate Oxide
20%
Integrated Circuits
20%
ESD Diode
19%
Time to Breakdown
19%
SOI Technology
18%
Reliability Diagnosis
18%
ESD Simulation
18%
On-chip ESD Protection
18%
Voltage Overshoot
18%
Recurrent Neural Network
18%
Measurement Results
18%
IEC 61000-4-2
18%
Trigger Voltage
18%
ESD Events
18%
NMOS
17%
Pulse Width
17%
Stress Conditions
17%
Transmission Line Pulsing
16%
Transmission Line Pulse
16%
On-resistance
16%
Hot Carriers
16%
Snapback
15%
Verilog
15%
Trigger Circuits
15%
Engineering
Electrostatic Discharge
94%
Protection Device
72%
Circuit Simulation
68%
Transients
65%
Metal-Oxide-Semiconductor Field-Effect Transistor
54%
Gate Oxide
49%
Electric Lines
40%
Integrated Circuit
30%
Silicon-Controlled Rectifier
29%
Power Supply
25%
SPICE
25%
Bipolar Transistor
22%
Dielectrics
22%
Breakdown Voltage
20%
Supply Voltage
20%
Trigger Circuit
19%
Recurrent Neural Network
19%
Figure of Merit
18%
Stress Condition
18%
Pulse Duration
18%
Interconnects
17%
Current-Voltage Characteristic
17%
Stress Pulse
17%
Simulation Result
16%
Induced Stress
16%
Rise Time
15%
Circuit Design
15%
Minority Carriers
15%
Q Factor
15%
Human Body Model
14%
Silicon Dioxide
13%
Interface Trap
13%
Transient Analysis
13%
VLSI Circuits
13%
Hot Electron
13%
Nanosecond
13%
Test Method
12%
Silicon on Insulator
12%
Design Guideline
12%
Noise Analysis
12%
Metrics
12%
Induced Noise
11%
Extractor
11%
Boundary Element Method
11%
Electromigration
11%
Circuit Performance
11%
Temperature Profile
11%
Gate Dielectric
11%
Circuit Model
10%
Good Agreement
10%
