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  • 2009

    A routing approach to reduce glitches in low power FPGAS

    Dinh, Q., Chen, D. & Wong, M. D. F., 2009, Proceedings of the 2009 International Symposium on Physical Design, ISPD'09. p. 99-105 7 p. (Proceedings of the International Symposium on Physical Design).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • BlueShift: Designing processors for timing speculation from the ground up

    Greskamp, B., Wan, L., Karpuzcu, U. R., Cook, J. J., Torrellas, J., Chen, D. & Zilles, C., 2009, Proceedings - 15th International Symposium on High-Performance Computer Architecture, HPCA - 15 2009. IEEE Computer Society, p. 213-224 12 p. 4798256. (Proceedings - International Symposium on High-Performance Computer Architecture).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior

    Wan, L. & Chen, D., 2009, Proceedings of the 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers, ICCAD 2009. p. 172-179 8 p. 5361295. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • FastYield: Variation-aware, layout-driven simultaneous binding and module selection for performance yield optimization

    Lucas, G., Cromar, S. & Chen, D., 2009, Proceedings of the ASP-DAC 2009: Asia and South Pacific Design Automation Conference 2009. p. 61-66 6 p. 4796442. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Open Access
  • FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs

    Papakonstantinou, A., Gururaj, K., Stratton, J. A., Chen, D., Cong, J. & Hwu, W. M. W., 2009, 2009 IEEE 7th Symposium on Application Specific Processors, SASP 2009. p. 35-42 8 p. 5226333. (2009 IEEE 7th Symposium on Application Specific Processors, SASP 2009).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • FPCNA: A field programmable carbon nanotube array

    Dong, C., Chilstedt, S. & Chen, D., 2009, Proceedings of the 7th ACM SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA'09. p. 161-170 10 p. (Proceedings of the 7th ACM SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA'09).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation

    Cromar, S., Lee, J. & Chen, D., 2009, 2009 46th ACM/IEEE Design Automation Conference, DAC 2009. Institute of Electrical and Electronics Engineers Inc., p. 838-843 6 p. 5227038. (Proceedings - Design Automation Conference).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Open Access
  • High-performance CUDA kernel execution on FPGAs

    Papakonstantinou, A., Gururaj, K., Stratton, J. A., Chen, D., Cong, J. & Hwu, W. M. W., 2009, ICS'09 - Proceedings of the 23rd International Conference on Supercomputing. p. 515-516 2 p. 1542357. (Proceedings of the International Conference on Supercomputing).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Reconfigurable circuit design with nanomaterials

    Chen, D., Chilstedt, S. & Deming, C., 2009, Proceedings - 2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09. p. 442-447 6 p. 5090706. (Proceedings -Design, Automation and Test in Europe, DATE).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Variation aware routing for three-dimensional FPGAs

    Dong, C., Chilstedt, S. & Chen, D., 2009, Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009. p. 298-303 6 p. 5076424. (Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Workload adaptive shared memory multicore processors with reconfigurable interconnects

    Akram, S., Kumar, R. & Chen, D., 2009, 2009 IEEE 7th Symposium on Application Specific Processors, SASP 2009. p. 7-14 8 p. 5226329. (2009 IEEE 7th Symposium on Application Specific Processors, SASP 2009).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • 2008

    Efficient ASIP design for configurable processors with fine-grained resource sharing

    Dinh, Q., Chen, D. & Wong, M. D. F., 2008, FPGA 2008 - Sixteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. p. 99-106 8 p. (ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • VEBoC: Variation and error-aware design for billions of devices on a chip

    Akram, S., Cromar, S., Lucas, G., Papakonstantinou, A. & Chen, D., 2008, 2008 Asia and South Pacific Design Automation Conference, ASP-DAC. p. 803-808 6 p. 4484062. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Open Access
  • 2007

    DDBDD: Delay-driven BDD synthesis for FPGAs

    Cheng, L., Chen, D. & Wong, M. D. F., 2007, 2007 44th ACM/IEEE Design Automation Conference, DAC'07. Institute of Electrical and Electronics Engineers Inc., p. 910-915 6 p. 4261313. (Proceedings - Design Automation Conference).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • GlitchMap: An FPGA technology mapper for low power considering glitches

    Cheng, L., Chen, D. & Wong, M. D. F., 2007, 2007 44th ACM/IEEE Design Automation Conference, DAC'07. Institute of Electrical and Electronics Engineers Inc., p. 318-323 6 p. 4261198. (Proceedings - Design Automation Conference).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Hardware acceleration for sparse fourier image reconstruction

    Dinh, Q., Bresler, Y. & Chen, D., 2007, ASICON 2007 - 2007 7th International Conference on ASIC Proceeding. p. 1346-1351 6 p. 4415887. (ASICON 2007 - 2007 7th International Conference on ASIC Proceeding).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • High-level power estimation and low-power design space exploration for FPGAs

    Chen, D., Cong, J., Fan, Y. & Zhang, Z., 2007, Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007. p. 529-534 6 p. 4196086. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Open Access
  • Performance and power evaluation of a 3D CMOS/Nanomaterial reconfigurable architecture

    Dong, C., Chen, D., Tanachutiwat, S. & Wang, W., 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design, ICCAD. p. 758-764 7 p. 4397357. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains

    Cheng, L., Chen, D., Wong, M. D. F., Hutton, M. & Govig, J., 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design, ICCAD. p. 370-375 6 p. 4397292. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • 2006

    A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction

    Cheng, L., Deng, L., Chen, D. & Wong, M. D. F., 2006, 2006 43rd ACM/IEEE Design Automation Conference, DAC'06. Institute of Electrical and Electronics Engineers Inc., p. 117-120 4 p. (Proceedings - Design Automation Conference).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Interconnect-driven nanoelectronic circuits

    Haruehanroengra, S., Chen, D. & Wang, W., 2006, Proceedings of the 2006 49th Midwest Symposium on Circuits and Systems, MWSCAS'06. p. 694-698 5 p. 4267450. (Midwest Symposium on Circuits and Systems; vol. 2).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Optimality study of resource binding with multi-Vdds

    Chen, D., Cong, J., Fan, Y. & Xu, J., 2006, 2006 43rd ACM/IEEE Design Automation Conference, DAC'06. Institute of Electrical and Electronics Engineers Inc., p. 580-585 6 p. (Proceedings - Design Automation Conference).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Optimal simultaneous mapping and clustering for FPGA delay optimization

    Lin, J. Y., Chen, D. & Cong, J., 2006, 2006 43rd ACM/IEEE Design Automation Conference, DAC'06. Institute of Electrical and Electronics Engineers Inc., p. 472-477 6 p. (Proceedings - Design Automation Conference).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • 2005

    Optimal module and voltage assignment for low-power

    Chen, D., Cong, J. & Xu, J., 2005, Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005. Institute of Electrical and Electronics Engineers Inc., p. 850-855 6 p. 1466475. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; vol. 2).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Web based distributed computing environment for nanotechnology

    Chen, D., Raghunathan, A., Mashl, J., Chiu, S., Parker, S., Aluru, N. & Jakobsson, E., 2005, 2005 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2005 Technical Proceedings. Laudon, M. & Romanowicz, B. (eds.). p. 720-723 4 p. (2005 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2005 Technical Proceedings).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • 2004

    Delay optimal low-power circuit clustering for FPGAs with dual supply voltages

    Chen, D. & Cong, J., 2004, Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04. Association for Computing Machinery, p. 70-73 4 p. 2.1p. (Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Open Access